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AD9910 25Mhz Crystal Settings How To?

Category: Hardware
Product Number: AD9910

The AD9910 data sheet is not specific in a number of areas that seem important, but maybe I'm missing something. First of all, it references a clock multiplier of either 20x or 100x, but does not give any indication of how this is changed. Also, as far as using a crystal as the ref clock, it does not give any indication of how or if the PLL should be used or how to set the clock/PLL registers. Also if there was a 20x multiplier on the suggested 25Mhz crystal that would only give a 500Mhz clock... would that not be half of the rated speed? Is there a way to get the full 1 GSPS out of a 25Mhz crystal.

The main question is how should the chip be set up to use the 25Mhz crystal? Register values? Should the PLL even be turned on if I don't really need the refclk_out output?

What about just driving the pins with a differential 50Mhz source with the 20x multiplier, would that give me the full 1Ghz clock? Would that require setting up the PLL and the loop filter. If I use a micro or FPGA to drive this, what would be the optimal clocking setup? I suppose with the PLLs on most micros and FPGAs it would be easy to get almost any clock signal to the chip.

I was hoping to not get the eval board and just build my own and write some software. It would be nice if I did not have to use the PLL and set up the loop filter at all.

  • Hi  ,

    I understand you have lots of questions about the AD9910. Let me break your questions into smaller segments for me to address each one of them.

    1. You're right that the clock multiplier is either 20x or 100x. This can be done by enabling PLL and then setting the multiplier by either 20 or 100x. Data sheet just showed that anything in between 20 or 100 still shows the same typical phase noise at -140dBc/hz.
    2. If you're using the crystal oscillator as reference clock here's the guide.

    To enable the crystal mode, switch the jumper, W7, to the XTAL mode. Remove C51 and 52. Place 0 (zero) Ω resistors at R4 and R11 on the backside of the board. The crystal oscillates at 25 MHz.

    External Clock inputs the operating frequency of the external reference clock or crystal. The maximum reference clock frequency of the AD9910 is 1 GHz. The default setting is 100 MHz. A red outline indicates that the value entered is out of range. Enable Multiplier selects the PLL multiplication factor (12× to 127×) by which to scale the input frequency. The default setting of this box is disabled (check box cleared), indicating that the reference clock multiplier circuitry is bypassed and the reference clock/crystal (REFCLK) input is piped directly to the DDS core.

    This AD9910 Evaluation Board Guide might help you more. Page 16 of the user guide will give you a detailed instructions on Configuring the Reference Clock Path .

    1. The 25MHz crystal when selected with the 20x multiplier gives 500MHz external clock and 250MHz system clock. Getting the 1GSPS can be achieved even if you're using 25MHz as reference clock. Just enable the PLL and set the multiplier to 40 to achieve the 1,000 MHz system clock. 
    2. Driving a differential 50Mhz source with a 20x multiplier will give you a 1GHz clock. Since your parameters really required PLL I highly suggest you install the external PLL loop filters as it gives more flexibility to optimize the PLL performance. The PLL and external loop filter components are shown in figure below:

    Full details on the components can be found and formulas can be found on the page 26 of the AD9910 data sheet.

    All the best,


  • The 20x or 100x PLL multiplier values you refer to are merely the two settings we used in the test configuration for specifying the residual phase noise of the DAC in the specifications table. The PLL multiplier supports integer multiplication factors from 12x to 127x (see the Phase-Locked Loop (PLL) Multiplier section for details).

    Also, see Figure 30, which is a block diagram of the entire clock input section. The diagram includes the PLL along with all the necessary controls and associated programming registers (including the specific bits within those registers).

    Note that the left hand side Figure 30 shows the REFCLK input that routes through a 1-of-3 demux to allow connection to a specific input path. The top path is the crystal resonator path, which incorporates an internal oscillator circuit. Note that the crystal path forces you to use the PLL. The middle path is the direct clock input path to the PLL for driving the PLL with an external clock source. The bottom path bypasses the PLL, which allows you to drive REFCLK directly with up to a 1GHz external clock source.

    Unfortunately, there is an error in Figure 30. There should be an arrow that points from the bottom of the REFCLK INPUT SELECT LOGIC block to the top of the demux. The implication being that the path is automatically selected via the demux as a the result of the logic level at the XTAL_SEL pin and the state of the PLL Enable bit (CFR3[8]).

    If you can provide a high-frequency (up to 1GHz) clock source to the REFCLK inputs, it is easier to work with the part because you can bypass the PLL altogether. Otherwise, as Jules points out, you will need to provide the appropriate external loop filter components as well as properly program all the pertinent PLL parameters. I presume there are commercially available oscillators that can provide 1GHz directly, if you decide to go the "direct clock" route.

    One advantage to having an Evaluation Board (EVB) is that you can use the EVB GUI to get the part set up the way you want and then save the setup file. The setup file reveals all the register settings specific to the setup. Another advantage of having an EVB is that it provides a common platform for assisting you with debugging your setup.