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Hello,

I am using a designed PCB with 2 AD9910 DDS chips.

I'm experiencing some peculiar behaviour at the output, so I want to ask some questions.

I'm using a 1GHz sinusoidal clock.

1. Am I supposed to get a mirrored signal at the unfiltered output?

When I program it to act at 400MHz, I also get a 600MHz signal. Is this due to digital aliasing?

2. I'm currently using a 1.5:1 transformer to change the differential signal to a single output.

The differential side is impedance matched to be 100ohm, and the output is 50ohm by the PCB stackup.

Am I impedance matching the circuit correctly? And can this be the cause of any intermodulation?

3. I'm experiencing 2nd(200MHz=600-400) and 3rd order(Also 200MHz=400-(600-400), for a different reason) intermodulation between the intended (400MHz) signal and aliased (600MHz) signal.

Assuming the filter is passive (which it is), what can be the possible reasons for this nonlinearity?

4. Does clock power have any effect on the behaviour of the DDS output?

Parents
• Hi there,

1. Digital aliasing is the effect when new frequencies appearing in the sampled signal after reconstruction which were not present in the original signal. It can be also caused by either: too low sample rate for sampling a particular signal or too high frequencies present in the signal for a particular sample rate. You should be seeing mirrored signal at the unfiltered output.

1. Upon checking on the values that you have given, Rint = 100Ω while RL= 50Ω and is using 1.5: 1 transformer. Based on these given values, the impedance didn’t match. You must change the values for this. If we remain RL= 50Ω then we must use Rint = 22.2Ω. However, if we use Rint = 100Ω we need to use RL= 225Ω.

This is the equation for impedance matching:

k = √(RL / Rs)

Any linear-time invariant system does not cause any intermodulation. There will be just difference in the phase and amplitude given that the input frequency is still the same at the output. Only difference in phase and amplitude will happen given that scenario.

1. Possible reasons for nonlinearity include:
• The use of passive filter. No amplifying element was used in the passive filters thus it offers low signal gain. Thus, comparatively lower signal than its input is expected at the output
• Nonlinear systems do not depend on its input. Its output is not directly proportional to its input.
1. A faster clock requires more power. Voltage required is affected significantly more than clock speed. Thus, in general, the higher the speed the more voltage it requires. But clock power does not affect the output in some ways. So, to answer your question, it would be NO. Clock power does not affect the behavior of the DDS output.
• Thank you.

I have some more questions about transformer impedance. I'm considering changing the transformer to ADT-1T-1P+(1:2 ratio), and have the secondary coil on the differential side. If I want the output load to be 50ohm, am I correct to have each resistor on the differential side to have 100ohm to have 200ohm in total?
The evaluation board for the transistor states I have two 50ohm resistors to have 100ohm in total, and I don't understand why if impedance depends on turn number squared.https://www.minicircuits.com/pcb/WTB-430_P02.pdf is the evaluation board pdf link.

• The ADT-1T-1P+ has an impedance ratio (Zr=Zs/Zp) of 2. That is, Zs:Zp = 2:1. The impedance ratio and turns ratio relate as: Nr=sqrt(Zr)=sqrt(Zs)/sqrt(Zp). Written in ratio form: sqrt(Zs):sqrt(Zp), or sqrt(2):1, in this case.

However, the transformer PRI and SEC are used in reverse in this application. In keeping with the application, Ns and Np, as follows, denote the "new" secondary and primary, per the application. Thus, the turns ratio (Ns:Np) is 1:sqrt(2). By convention, Np=1, so Ns:Np becomes, (1/sqrt(2)):1.

This means that if you want the impedance reflected on the filter side (the new secondary) to be 50Ω, then each of the resistors on the IOUT_P/N side (the new primary) must be 50Ω.

You might find this Application Note helpful.

Technically, regarding the AD9910 Evaluation Board, the 50Ω resistors on the DDS side the of transformer should have been 25Ω each for a proper impedance match to the 50Ω on the filter side. However, there appears to be little to no degradation in spectral characteristics of the output signal even with the impedance mismatch.