AD9957 Sync State Preset Value

Hi all,

Our customer will start to design with AD9957.

We have the question about the Multichip Sync Register ,Address 0x0A.
[23:18] Sync State Preset Value ; Default is 000000b.
This 6-bit number is the state that the internal clock generator assumes when it receives a sync pulse.

There is no detailed explanation in the data sheet on how to design the value of "Sync State Preset Value".
Please give me some advice on how to consider, calculate and design.

Best Regards,

  • There is nothing innately special about the sync value. Typically, all AD9957s in a synchronized system will use the default value. Normally, there is no reason to change the value.

    In the data sheet, Figure 55 provides some insight into the function of the sync value. The programmed value (default = 0), presets the R divider synchronous with the sync pulse. Note the sync pulse originates from the SYNC_IN pins (see Figure 57). The CLOCK GENERATOR in Figure 57 is essentially the R divider in Figure 55. In a typical synchronized system, the expectation is that the clock tree for the digital base band circuitry (CCI filter, half-band filters, etc.) is in lock step across all devices. The sync value gives the user the ability to skew the relative timing of the digital base band circuitry between devices. That is, PDCLK can be skewed in time relative to other devices in the multichip system. Although I cannot think of a reason one might want to do this, the option is there.