Our customer will start to design with AD9957.
We have the question about the Multichip Sync Register ,Address 0x0A.
[23:18] Sync State Preset Value ; Default is 000000b.
This 6-bit number is the state that the internal clock generator assumes when it receives a sync pulse.
There is no detailed explanation in the data sheet on how to design the value of "Sync State Preset Value".
Please give me some advice on how to consider, calculate and design.