AD9959 Input termination scheme


I want to provide LVDS input to AD9959 IC but in datasheet I could not find any detail regarding this.

Will this IC support LVDS as input clock source, if so how to provide the LVDS input to the chip.



  • 0
    •  Analog Employees 
    on Apr 12, 2021 1:22 PM

    The AD9959 REFCLK input, when configured for input buffer mode (that is, not for crystal resonator mode), functions as a general purpose differential receiver. A simplified schematic of the REFCLK input is shown in Figure 31 of the data sheet (pg. 17).

    Because the receiver has an internal 1.15V common mode bias level, it cannot operate directly with an LVDS driver as an input. Furthermore, the specified minimum input voltage swing on the REFCLK input is 400mV pk-pk (200mV pk), which just barely supports LVDS voltage swing. At the very least, you must ac-couple the LVDS driver to the REFCLK pins (to avoid disturbing the internal 1.15V bias). Even so, the low output voltage swing of LVDS may not be sufficient to reliably toggle the REFCLK receiver.

    A better approach is to use a level shifting buffer to convert LVDS to a more suitable output level for the REFCLK input.