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AD9837 FSK Code Signal Generation without any MCLK delay


As per application note AN-1070, "A signal appears at the output of the DAC seven MCLK cycles after RESET is set to 0." . But for my application, i want to generate FSK code with each 1mS width with 10 bit word. For example, i want to generate code equivalent to "1010110011", let frequency f1 represent "1" and f2 for "0". Then DAC output should be f1f2f1f2f1f1f2f2f1f1 without any clock delays in between. Is the same possible using above IC and if so , how the control signal or register control to be incorporated.

[edited by: Bivin at 8:15 AM (GMT -4) on 22 Mar 2021]
  • Have you read the datasheet and are you following it?

    In particular:

    To change the entire contents of a frequency register, two consecutive writes to the same address must be performed because the frequency registers are 28 bits wide. The first write contains the 14 LSBs, and the second write contains the 14 MSBs. For this mode of operation, the B28 control bit (Bit D13) must be set to 1. An example of a 28-bit write is shown in Table 10

    Note, however, that continuous writes to the same frequency register may result in intermediate updates during the writes. If a frequency sweep, or something similar, is required, it is recommended that users alternate between the two frequency registers


    In an FSK application, the two frequency registers of the AD9837 are loaded with different values. One frequency represents the space frequency, and the other represents the mark frequency. Using the FSEL bit in the control register of the AD9837, the user can modulate the carrier frequency between the two values.

    It is all there ... you just need to read it and implement it. If you are following this there should be no need to perform a RESET between frequency changes to support FSK.

  • Hi

    Thanks for the reply. What would be the worst delay in switching between frequencies using FSEL bit ?

  • Look at the datasheet; Figure 3 and CONTROL REGISTER in page 13.

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