As per application note AN-1070, "A signal appears at the output of the DAC seven MCLK cycles after RESET is set to 0." . But for my application, i want to generate FSK code with each 1mS width with 10 bit word. For example, i want to generate code equivalent to "1010110011", let frequency f1 represent "1" and f2 for "0". Then DAC output should be f1f2f1f2f1f1f2f2f1f1 without any clock delays in between. Is the same possible using above IC and if so , how the control signal or register control to be incorporated.
[edited by: Bivin at 8:15 AM (GMT -4) on 22 Mar 2021]