AD9957 BFI mode problem

Hello,

   I'm looking for a help in setting up AD9957 in BFI mode.

I've build my own project in which AD9957 is controlled though BFI interface by ZYNQ7000. Unfortunately I can't run properly AD9957 in BFI mode. When I set SINGLE TONE MODE device works fine, but when I set QDUC BFI mode I get on output very noisy signal. I tried different settings but no success. In BFI mode I have constant high level on pin CCI_OVFL even after resetting CCI by set CLEAR CCI bit in CFR1. Does it mean that input I/Q stream is wrong ?

My settings are :

  • CFR1 = 0x 00 00 00 02 // I use 3-wire SPI interface
  • CFR2 = 0x c0 01 08 60 // LSB first in BFI interface
  • CFR3 = 0x 11 18 c1 2a // REF_CLK input is 25MHz from ZYNQ ; output PLL : SYSCLK = 525 MHz
  • DAC register (0x03) = 0x 00 00 00 7f
  • Profile 0 QDUC (0x0e) = 0x fd 7c 00 00 05 05 00 00 // R=63 ; OSF = 0x7c ; ad9957 output frequency = about 10 MHz

As I/Q stream I use sin and cos waves with small amplitude, coded as 2'complement and frequency about 0.5 kHz.
On the first picture there is output signal from AD9957 and its FFT. Live signal is very noisy and live FFT is also not as good as on the picture.


On the second picture there are BFI interface signals grabbed inside ZYNQ:

  • sin wave value
  • cos wave value
  • I stream
  • Q stream
  • TxEnable
  • PDCLK

I don't use any SYNC signals in AD9957.
I've read about SPORT interface but still I do not know how it refers to ad9957.
Can anyone explain how exactly should look BFI signals and delay requirements between them for AD9957? Information in AD9957 pdf is not detailed.
Maybe someone can show screenshot from real BFI signals coming into AD9957.

Thanks in advance for any suggestion,
Piotr

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  • Hello again,

       I think, I've solved my problem.Grinning

    Here is what I've done.
    First,I misunderstood meaning of DATA ASSEMBLER HOLD LAST VALUE bit in CRF2. I thought that it is active only when TXENABLE signal is inactive, but it's not true. This bit is valid as long as it is set.
    Second, during start-up AD9957 I set two times bit CLEAR CCI in CFR1.
    I also multiplied length of active TXENABLE signal, so I've got pure output signal from AD9957.
    I hope this information will be helpful for others who have similar problem.

    Any comments ?

    Thank you,
    Piotr

Reply
  • Hello again,

       I think, I've solved my problem.Grinning

    Here is what I've done.
    First,I misunderstood meaning of DATA ASSEMBLER HOLD LAST VALUE bit in CRF2. I thought that it is active only when TXENABLE signal is inactive, but it's not true. This bit is valid as long as it is set.
    Second, during start-up AD9957 I set two times bit CLEAR CCI in CFR1.
    I also multiplied length of active TXENABLE signal, so I've got pure output signal from AD9957.
    I hope this information will be helpful for others who have similar problem.

    Any comments ?

    Thank you,
    Piotr

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