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AD9911 - auto clear phase accumulator by change in the profile pins

Dear ADI experts,

I have been working on the auto clear of the accumulator by a change of a profile pin for a couple of days now. The clearing of the phase works well after a high pulse on the IO_Update pin, but not on changes of a profile pin. I really checked timing w.r.t. sync clock, SPI communication and read the data sheet multiple times. Still no success.

Now I found a remark in the following post

It states:

"In most of ADI's DDSs, a profile change is equivalent to issuing an IO_UPDATE, however not in the multi-channel DDS (AD9958 or AD9959). Page 27 under Clear and Release Bits is in error, only the IO_UPDATE does the clearing, not a profile pin change."

The AD9911 looks quite similar to AD9959. Is clearing the phase accumulator by profile pin change not possible for the AD9911, too??

Could you please correct the data sheet in that case?!

Kind regards,

Dipl.-Ing. Sven Probst.

Corrected typo
[edited by: swapro at 2:52 PM (GMT -5) on 14 Jan 2021]
  • Some more investigation results:

    For 2 level frequency modulation there is a clear of the accumulator for each toggle of the P1 pin. Unfortunately the timing of the clear seems to be 5 SysClks earlier than the update of the FTW. The clearing might work well with phase modulation, which has a lower latency of 29 SysClk cycles vs. 34 for FM.

    With 4 and 8 level modulation (FM) the auto clear is not working on profile pin changes.

  • Hi,

    It may have been a carryover from another data sheet and that detail wasn't caught. The profile pin change does not invoke the clear accumulator function. It requires assertion of IO_Update. In this case, the data sheet will be updated to reflect this correction.

    Best regards,


  • Hi Mark,

    thank you for the clarification!

    Strange thing is, that there is an auto clear by pin change for the 2 level modulation ...

    A working solution for me is as following (for others maybe interesting):

    • FM modulation with 8 levels (thus no clear by pin change)
    • 100MHz reference clock, PLL divider 4: DDS clock is 400MHz and SyncClk is 100MHz.
    • external logic to detect pin change (e.g. SN74AUC logic)
    • change of profile pins is synchronized to SyncClk by egde triggered register (e.g. SN74AUC16374)
    • IO_Update gets set to one with a delay of one SyncClk cycle w.r.t. change of pins (after synchronization)

    It looks to me, that the internal latency of IO_Update is one sync clock less than the latency of the frequency profile change. The next prototype will be tested on Monday - it is hopefully the last one till production.

    Kind regards,