AD9959 QSPI 200 MHz Termination

Hi Niklas,

While we can't recommend a proper layout/termination guideline for an SPI port running at such clock speeds that is documented by ADI, we are certain that the SPI port uses CMOS I/O logic. It would be useful to adhere to standard practices in high-speed CMOS logic design and layout. I would like to recommend this document for your reference: 

Mixed-Signal and DSP Design Techniques, Hardware Design Techniques (analog.com)

The discussion at section 10.58 about "Dealing with High Speed Logic" might be helpful.

Furthermore, please be guided that the maximum SCLK rate of 200MHz only applies for write operations. Read operations are not feasible at the 200 MHz SCLK rate as it is limited by the minimum data valid time specification, 12ns. You will have to implement a bi-directional data transfer running at two different frequencies: write at 200MHz and read at about 50MHz.

Best Regards,
Mars

Hi Mars,

Thank you for your answer. It was really helpful to me.

Best Regards,

Niklas