AD9851 DDS output connections and refclock

Hi,
I am using the AD9851 in a scalar network analyzer and have some questions about the operation.
The frequency range I work in is ~2 MHz to 60-70 MHz and I am looking at LPF designs to put on the IOUT pin. I found the filter layout of the evaluation board:

Could someone explain the impedance termination? Does it not need a resistor in series with the signal as well, directly on the chip IOUT pin? The 200 ohm resistors R6 and R7 together form a 100 ohm DC to 200 ohm HF termination. If I wanted to use this DDS chip for 1Vpp do I just change these values to 100 ohm resistors?

I read that the elliptical LPF introduces ripple into both the pass band and stop band, but provides very steep attenuation. Can I simply take this LPF design or are there better options? I am planning on using a 180 MHz crystal oscillator as the REFCLK (so without 6x multiplier), but I am not sure if this has any benefits compared to a 30 MHz crystal with multiplier. From what I read in the datasheet of the AD9851 images can occur at the REFCLK +/- the frequency of interest. My maximum frequency is around 60 MHz, so that would mean that my first image is 120 MHz (correct?). I can imagine that if that is the case I can use a filter that has a slightly less steep drop off but no ripple in the pass band (e.g. Inverse Chebyshev). Does this make sense?
I am looking forward to your answer!
Many thanks in advance,
Cheers,
Rens

  • 0
    •  Analog Employees 
    on Jan 13, 2021 7:20 AM 1 month ago

    Hi Rens,

    Based on the setup and output that you desire, you can use the same schematic as the evaluation board. The evaluation board was designed to have optimum performance up to 70.1MHz as shown in the typical performance characteristic of the data sheet. For the filter response, you can use the ADIsimDDS to simulate the output performance of different filters.

    Best regards,

    Mark

  • Hey Mark,
    Thanks for the reply!
    I was looking around for a suitable high speed opamp for amplfication of the DDS output up until 50MHz and ran into lots of instabilities. Would it be advisable to adjust the signal level (Vp-p) via the Rset resistance instead of an external amplification stage? Provided I do not need to change the signal level often.

    Plus I still wonder if there is an advantage to using a 180 MHz crystal instead of a 30MHz with 6x multiplier.

    Thanks in advance for your input!

    Cheers,

    Rens

  • 0
    •  Analog Employees 
    on Jan 14, 2021 7:52 AM 1 month ago in reply to Xerrorable

    Hi Rens,

    It is advisable to adjust the signal level via Rset if it will be able to meet your application. As for the 180MHz crystal instead of 30MHz with 6x multiplier, TPC 10 and 11 on the data sheet shows the output phase noise comparison for both setup.

    Best regards,

    Mark

  • 0
    •  Analog Employees 
    on Jan 14, 2021 2:15 PM 1 month ago in reply to mcee

    Regarding Rset:

    Although you can adjust the output level by decreasing Rset, you must ensure that the resulting voltage that appears at each of the DAC output pins stays within the specified voltage compliance range of -0.5V to +1.5V.

    Regarding a 180MHz crystal:

    The REFCLK input of the AD9851 is a logic input, so it cannot support direct connection of a crystal resonator. However, a crystal oscillator is suitable as long as its output level meets the input voltage specifications of the REFCLK pin. 

  • Hi Kenny,
    Thanks for the useful additions.
    Could you elaborate a little more on the voltage compliance range?
    The DAC outputs a current set by Rset which has to be converted to a voltage.
    Does this mean that we are limited to converting the current (e.g. 10 mA) to 1 Vpp (-0.5V to +0.5V Sine) by a 100 ohm resistor? This would also mean that we can't set a 2 Vpp (centered at +0V DC) since this violates the -0.5V compliance range?

    Regarding the REFCLK input I use a +5V supply to power the AD9851 and my clock oscillator (I should've been more clear, sorry) is powered by +3V3. In principle it cannot meet the input voltage specification of the REFCLK pin, but its output is of the CMOS kind. Does that mean (according to note 2) that it should still be able to reliably clock the AD9851?

    Cheers,
    Rens