AD9910 optimum Open Loop Bandwidth

Hi ADI tech support,

Could you please let me know the optimum Open Loop Bandwidth under following condition?

Target device: AD9910
Clock input: 25MHz crystal
Multiplier: 20
System Clock: 500MHz (= 25MHz x 20)
DDS output frequency: 27.12MHz +/-10% in 1Hz step, no modulation CW only

Will set Phase margin 60degree,
Charge pump current to be selected to get close to E24 CRs.

I am get used to use PLL Loop Filter Tool.

Best Regards,

  • Hello ADI tech support,

    Could you please respond to my question?


  • +1
    •  Analog Employees 
    on Dec 9, 2020 9:09 AM in reply to katsu

    Hi Katsuhiro,

    Apologies for the late response for your thread have been overlooked.

    Optimum loop bandwidth must be assessed according to the phase noise of the external reference source and the PLL VCO. Narrowing the loop bandwidth suppresses more of the phase noise that originates with the reference (in this case, a quartz crystal resonator) while widening the loop bandwidth allows more of the reference phase noise to pass through the PLL. With this, if the phase noise of the PLL VCO is quite good, there can be performance benefit for using a narrow loop bandwidth (assuming that the reference phase noise is not so good). On the other hand, if the phase noise of the PLL VCO is not that good, it can be beneficial to widen the loop bandwidth to suppress more of the VCO noise (assuming that the reference phase noise is good).

    Then there is the issue of stability, which relates to phase margin. High phase margin yields better stability at the expense of longer lock times. So, there is a tradeoff to made be here, too.

    Finally, in the context of the integrated PLLs in our DDSs, they are more a "convenience" feature than a performance feature. The integrated PLL allows the use to get away with a low frequency reference (like a crystal), but with the phase noise tradeoffs associated with the integrated VCO. The integrated VCIs are good, but not of the high performance phase noise variety. That said, if phase noise is the primary performance parameter, then it is best not to use the internal system clock PLL.

    Best regards,


  • Hi Mark,

    Thank you for detailed explanation.
    VCO phase noise itself is not specified in the datasheet though, Figure 15 and 16 would be good reference. Will tune Loop Filter during evaluating developed circuit board.

    Best Regards,

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