I have a few questions about AD9914 DAC calibration procedure that I have not yet seen be answered:
- Should the calculated calibration time be applied between the two write cycles to CFR4 register or between the two IO_UPDATE pulses following each write?
- What is the tolerance of the calibration time to get the best possible results?
- What is the function of "DAC CAL clock power-down" bit in CFR4 and is it neccesary and/or can be used for DAC calibration?
- Should the DAC be calibrated immediately upon power up or after first setting the clock settings in CFR3 or both?
Thank you for your answers.
To answer your questions, you can apply the calculated calibration time between the two IO_UPDATE pulses following each write on CFR4 register. There is tolerance for the calibration time but Figure…
To answer your questions, you can apply the calculated calibration time between the two IO_UPDATE pulses following each write on CFR4 register. There is tolerance for the calibration time but Figure 23 of the AD9914 Data Sheet shows the required DAC Calibration Time value according to the SYSCLK rate. In addition, the specifications also indicates a maximum DAC calibration time of 135us. The DAC CAL Clock Power-Down bit can only be enabled when Bit 26 which is the Auxiliary divider power-down bit for the SYNC out circuitry. DAC CAL should be initiated after each power-up and every time the REF CLK or internal system clock is changed.
Thank you for your answer.
There is stil some confusion however.
According to figure 23 and the equation on page 20 the maximum calibration time (at f_sys = 500MHz) equals 939us. However the "Maximum DAC calibration time" specification on page 6 states 135us which is actually the minimum calibration time (at f_sys = 3500MHz) according to figure 23.
Is this simply a mistake on page 6 or is there something I don't understand?
The value on page 6 is only for a system clock of 3500MHz and figure 23 shows the maximum calibration time for each system clock frequency.