AD9910 Eval software RAM loading errors

Hello Thomas,

The fatal error appears to be a time out or runtime issue, when the system clock = 0 Hz.

For example, if you enable the Ref Clock Multiplier with a multiplication of 0 (default), the system clock goes to 0 Hz.  With your version of the software, you should be able to avoid the fatal error if you change the REF CLK multiplication value of 0 before you open the OSK / Digital Ramp Generator window. We'll fix the runtime issue in a future revision. Thanks.

I have attached a RAM file. I'm able to load and read this file with no problems. I've also attached the setup file I used with the evaluation board. I would run the setup file first and then the RAM file. The RAM file is 101 (32-bit) words in Raw Binary format. In addition, the RAM file is a frequency sweep from 20 MHz to 30 MHz. Let me know if you can consistently load and read this RAM file.

Hi Salman Dinani,

You also posted the same question in this thread: Synchronising the AD9910. Would it be okay if you start a new discussion for this inquiry?

First of all, for the single-tone mode operation, you can refer to the Single-tone Mode Section in the AD9910 Evaluation Board User Guide (page 9). Also, ensure you do a master reset before entering the settings on the evaluation software.

What value of REFCLK input are you using? Kindly take note that when you are using the PLL (REFCLK Multiplier is enabled), your REFCLK input must be within the specifications in the datasheet. In AD9910, it is defined to be 3.2MHz to 60MHz. But please make careful choice on multiplier value, so that your total System Clock would not exceed 1000MHz.

What I can advise is, we need to check first if your board is working okay. Kindly do the following first:

1. Power Supply connection has correct settings
2. REFCLK input is 1000MHz
3. Disable REFCLK Multiplier (leave the "Enable Multiplier" checkbox clear)
4. Check "/2 Divider Disable" checkbox so that your System Clock (Fs) is 1000MHz
5. Change Output Freq on Profile 0 to 10MHz.
6. Then LOAD.

     You should be able to get a 10MHz filtered output at J4.

You can you also send us your AD9910 register map settings. That way, we can set it up in the lab to compare results.

To do this:

• set-up your board (power supply, master clock, etc)
• click the RESET (Master Reset) button.
• input your configuration.
• go to file>save setup.

You can then forward us the set-up files (.stp).

Hope this helps.

Best Regards,

Sitti

Message was edited by: sittie aisha magayo-ong added steps to check if board is okay.

Hi

I am using AD9910 evaluation kit. when I use PLL multiplication block and try to generate a single tone frequency. Initially there was no wave at the output but when I check the "PFD X reset" block then the output appears. But the output frequency is about 1.55 times greater then the desired frequency. for e.g 10 MHz comes out to be 15.5 MHz and 70 MHz comes out to be 108.5 MHz etc.

Please tell me am I missing some thing or configuring board wrong?

Thanks in advance...

Regrads

Salman Dinani

Hi Sitti

Thanks for correcting me, I will start a new discussion where i will put my problem in detail

Regrads

Salman Dinani

Hi Sitti

Sorry for replaying on this link again, I have started a new discussion yesterday but no one yet replayed so I am asking here in hope of getting any solution.. I am posting my query from that discussion https://ez.analog.com/thread/17455 .

Hi

I am using AD9910 evaluation. Before coming to my original problem of chirp generation, as a new user of this evaluation kit I have observed some thing of which I have no explanation. kindly guide me :

• I am providing the external Reference clock to my board, and used PLL multiplier block "without populating loop filter components on Kit" (because I didn't knew at that time) and tried to generate a single tone wave form and I got nothing on output (as it should be because there are no filter component installed) but when I checked the "PFD X Reset" block surprisingly I started to got the output frequencies which are about 1.55 times the desired frequency which I had specified in the GUI (for e.g. 10 MHz appears to be 15.55 and 70 MHz appeared as 108.5 MHz etc..).

1. After reading through different experts comment, for using PLL multiplier there has to be a loop filter..so without connecting loop filter, this type of output is just a coincidence or a functionality of which I have no information?

   2. I tried to generate chirp signal using only external reference clock (NO PLL multiplier, clk divider disabled) via DRG and OSK mode with these specification

                                                            Ref clk= 80 MHz

          sweep 0= 0.001 MHz                                                    sweep 1=     5 MHz

          Rising step size= 0.01 MHz                                           Rising step size=  0.01 MHz 

          Rising step Interval= 0.003 us                                         Rising step Interval=  0.003 us

I specified the lower and upper frequencies for sweep and the rising step size,but I am not able to specify the rising step interval of my own choice. Software is putting some limit. Instead of 0.003us software itself changes it to 0.05 us. Is there any lower limit of rising step interval?

Thanks in advance

Regards

Salman Dinani

Hi Salman Dinani,

I apologize for the late response right after you posted a new discussion. I provided some answers on your new thread. I hope that helped.

Best Regards,

Sitti

Hi, I also had the same issues/doubts with the RAM. Could you help me where are the attached files that you're referring to, as I can't seem yo find them?