AD9833

Hi,

I am using AD9833 to generate a 134kHz square wave. MCLK=11.0092MHz. The output square wave does not have uniform period. Eight pulses have the same period and then the next one has slightly longer period. Later, I found out the difference is one clock cycle, or 91ns. It does not change with output frequency. I have tried from 10kHz to 150 kHz with the same results. Any ideas?

Tom

  • 0
    •  Analog Employees 
    on Jul 19, 2010 11:26 PM

    Hello Tom,

    I think I know the answer to your question, but you'll have to confirm it for me.  I think what you are seeing is the "nature of the beast", but let me explain.  The main element in my opinion of a DDS is the phase accumulator.  This accumulator continuously adds the frequency tuning word (FTW) over and over again and it is the rate at which this accumulator rolls over that sets the output frequency.  For a sine-wave output, this phase accumulator feeds into a phase-to-amplitude conversion block, but for a square wave output you can take and output the MSB of the phase accumulator.  This is what the AD9833 is doing, however there is a slightly better way which I will describe later.

    Since the phase accumulator usually doesn't stop on an exact multiple of your FTW before rolling over (only powers of 2 would), the period will be slightly less than what you asked for until those little bits left over add an extra MCLK cycle.  For example, say you're setting the output to be 3.3MHz, or 3/10 of your MCLK.  Starting at 0, the accumulator cycles 3/10, 6/10, 9/10, 2/10, 5/10, 8/10, 1/10, 4/10, 7/10, 0.  You'll notice the first two "periods" are 3 MCLK cycles while the third period is 4MCLK cycles.  It is the average of these periods, (2 * 3 + 1 * 4) / 3 = 10 / 3, that equals the period you specified.

    I've attached a quick spreadsheet I put together that might help.  It calculates what # of MCLK cycles you should see per period and what % of the time you'll see those periods.  The slightly better way than using the MSB of the phase accumulator is to use the sine-wave output and pass it through a comparator.  Some of our newer, higher speed DDS' have an on-chip comparator for this function instead of providing the MSB output.

    If my explanation is still slightly confusing I might recommend reading The DDS Tutorial which explain DDS operation in greater detail than my short two paragraph version.

    Kevin.G

    DDSMSBOut.xls
  • Hi Kevin,

    Thanks a lot for the quick answer. I was not expecting a quick answer because it seems to be a difficult question. It looks like the question fell to the right place! I think I understand what you are trying to tell me and will go over the tutorial later.

    We have two AD9833s in the design. Their MCLK pins are connected together so that they are in SYNC. One is used to generate sine wave output. The other is supposed to be a zero crossing output of the sine output with settable phase delay.

    So the sine wave output should have the same problem, isn't it? It is very difficult to see the problem with sine wave output on the scope. It looks like your recommendation is to use sine wave to generate the square wave. But if the sine wave itself has the problem, the generated square wave should not see any improvements. Plus a good zero crossing circuit is not very easy for our application because it must work over 1kHz to 150kHz. Do you have any other suggestions to solve the problem? We basically need a good programmable sine wave generator. Any other chips that may be better?

    Thanks a lot for your help!

    Tom Li

  • 0
    •  Analog Employees 
    on Jul 20, 2010 10:56 PM

    Hello Tom,

    One of my cohorts corrected me on something I mentioned.  It's not just powers of 2 that don't exhibit the slightly changing periods but any integer division of 2^28 won't do this.

    I don't think the sine-wave output experiences the behavior you're thinking of.  If you think about it, the sine output is using the 12 MSBs of the phase accumulator to calculate the amplitude so it's not transitioning from 0v to full-scale, but from some value just below 360 degrees to some value just above 0 degrees.  If properly filtered, this will be a relatively smooth transition where the zero-crossing is closer to desired period length.  Some of this is a little hard to describe.  The "phase wheel" mentioned in the DDS tutorial is a good explanation.

    I can't test your desired setup in the lab, but I can create an excel spreadsheet to try and plot the expected behavior.  I would have to use an ideal phase-to-amplitude conversion though (IE the sine function).

    Kevin

  • Kevin,

    Thanks. Let's use your earlier example: MCLK=10MHz, Output Frequency=3.3MHz. Square Wave Output = 3MCLK 3MCLK 4MCLK. One pulse will be 1MCLK longer than the other two. That is huge. If we change the output from square wave to sine wave, what will happen to the period? Your comments seem to suggest the difference in period will be less than 1MCLK. Is that a correct understanding? If yes, how much will be the "improvement"?

    Tom

  • 0
    •  Analog Employees 
    on Jul 20, 2010 11:25 PM

    Hey Tom,

    My example was on the extreme side so I could quickly explain why you are seeing the changing period length.  If you choose a much lower output frequency, like your 134KHz, the output will swap between 82 MCLKs and 83MCLKs which is less dramatic of a change (see the spreadsheet I attached).  The difference will always be 1 MCLK which is what I thought you said you were seeing.

    I can't say how much of an improvement passing the sine wave output through a comparator is over using the MSB output.  The best I can say or suggest is to just take a look at the output from your evaluation board.  Yes, I'm pretty sure the difference between periods should be much less than 1 MCLK period.  Maybe one my colleagues can add further comments?

    - Kevin