I am trying to interface AD9224 40 MSPS ADC to spartan 3 FPGA. I am generating 12.5 Mhz clock with FPGA and giving it to ADC as a sampling clock.What I observe that when I am feeding clock to ADC analog signal (which is to be sampled) attached to it gets very noisy. I went for analysis and found that the noise frequency is exactly that of ADC clock frequency. I had separate analog and digital ground which are shortedonly at the supply input.
My signal frequency is 40 kHz while sampling clock to the ADC is 12.5mHz.
I examined the FPGA clock not much of jitter is there. I totally suspect the analog and digital ground layout pattern. As mentioned by Fvm both have to be shorted directly under the ADC. I had them shorted at supply input. But can this cause such a serious problem. Later I put even a jumper to short both the grounds as near the ADC as possible but that too didnt help.One more thing I observed that even the supply for ADC is not switched ON..if I simply feed clock to ADC without having supply on..analog input gets noisy. I am using 50 ohm resisters in series with ADC analog input.
I’m sorry, EngineerZone doesn’t currently provide a support community for this particular Analog Devices product.
To get support on this product, I would suggest submitting your question to the Analog Devices support team in your region. You can find the appropriate support contact on our website at: http://www.analog.com/support
If no propertly data pulse concur with CLK may be grand noise at output.