Not sure how many time do AD9831 and AD9833 spend to change the output frequency? That is, if I want to change the output frequency, then what's the fatest timing for AD9831 and AD9833?
Hope I describe my questions clearly.
There are two possible questions I think you could be asking. Both are somewhat related. The first possible question could be "How long does it take the AD9831 or AD9833 to change it's output frequency after receiving the command?" Most DDS datasheets I know would list a spec in the Specifications section but I didn't see one listed in either datasheet. This question is probably best answered by LiamR.
The second possible question could be "How fast can I periodically update the output frequency?" This question I can answer. It depends on the communication interface (serial vs. parallel), the speed of the interface, and the number of bits and writes required to send the command.
The AD9831 has a 16-bit wide parallel interface where the register being written to is selected by 3 address pins. The max speed of the interface is 25MHz and a single frequency tuning word or FTW takes up two register. If you need to change the entire FTW it will take you two write sequnces so the max update rate is 12.5MHz. However, if you only need to modify the least significant bits, only one write is required and you can update the frequency at a rate of 25MHz.
The AD9833 has a serial/SPI interface that runs at a max of 40MHz. With this part, an entire FTW also takes up two registers, but it requires that a control register be written to first before writing the actual frequency value. Each register is 16-bits wide. Changing the entire FTW would take 3 x 16 / 40MHz = 1.2us which is a max update rate of 833.3KHz. If only changing the LSBs it would only take 2 x 16 / 40MHz = 0.8us which is an update rate of 1.25MHz. See page 15 of the AD9833 datasheet for examples of changing the frequency.
I think Kevin has covered this pretty comprehensively but just to comment once you load the data to the registers there is a 7/8 MCLK latency between the last FSYNC going high and actually seeing the change in output. The delay can be 7 or 8 MCLK cycles depending on the position of the MCLK rising edge when the data is loaded to destination register.