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ADF4350's SPI configration problem

hello:

       we want to use FPGA+ADF4350 to generate two high frequency clk(up to 2.4GHz),  ADF4350 can be configured in SPI bus standard.

As we know, there are four signals of SPI, but there only there for ADF4350'SPI.

We want to konw is the LE pin of ADF4350 is the same as cs pin of SPI bus standard?

The NIOS II software core is integrated in altera's FPGA, we can use SPI of NIOS II to config lots of ADI chips(AD9518 AD8322 and so on) with conveniency. Can we config ADF4350 in the same way(NIOS II SPI)?

SPI BUS standard ------------ ADF4350

   SCLK                --------------CLK(PIN1)

   CS                   --------------LE(PIN3)

   SDIO             ----------------DATA(PIN2)

   SDO             ---------------NO PIN

thanks!

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  • Hi huangming,

         The ADF4350 only implements a SPI compatible serial interface and all pins (CLK, DATA, and LE) are all inputs, i.e. there is no register read instruction and therefore no SDO (MISO) compatible pin. The signal on the  LE pin is analogous to the CS (SS) signal from an outside prespective. However, the LE signal is really a load signal which allows the serial data latched in the register buffer to be loaded into the actual register where it will alter the chips perfomance according to the datasheets register descriptions. It is active low, like CS, and you cannot latch data into the ADF4350's register buffer without an active LE signal, hence the analogous functionality to CS. Wiring your NIOS II signals in the manner described in your post and executing a write function will allow you to perform register writes on the ADF4350.

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  • Hi huangming,

         The ADF4350 only implements a SPI compatible serial interface and all pins (CLK, DATA, and LE) are all inputs, i.e. there is no register read instruction and therefore no SDO (MISO) compatible pin. The signal on the  LE pin is analogous to the CS (SS) signal from an outside prespective. However, the LE signal is really a load signal which allows the serial data latched in the register buffer to be loaded into the actual register where it will alter the chips perfomance according to the datasheets register descriptions. It is active low, like CS, and you cannot latch data into the ADF4350's register buffer without an active LE signal, hence the analogous functionality to CS. Wiring your NIOS II signals in the manner described in your post and executing a write function will allow you to perform register writes on the ADF4350.

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