Problems Using the AD9854 in Parallel Mode w/External I/O UD Clk

This is a lash-up using the AD9845 demo board along with a microcontroller board and a custom interface board.  Following this is a design that places the principal components on one custom board as a product design.  The interface board has series terminations in the parallel bus, and the four inch flat cable has a foil that is grounded for better impedance control.  The control technique uses microcontroller port bits in a bit-bang fashion since this design will be set up and not changed very frequently.  Obviously, the microcontroller does not come close to the I/O speed capacity of the DDS part.

After making observations with a digital scope, there is very little ringing on the parallel bus lines.  Data and Address are stable 100nsec before write strobes and much longer afterward.  The problem with using external I/O update pulses is that the part powers up in the internal I/O update mode, and getting it to switch to external mode involves writing to the four byte control register at address 1D thru 20.  The specific bit is the LSB of address 1F, which must be written low to switch to external mode.  The microcontroller port tied to the I/O update signal initializes as an input port with a weak pullup on the microcontroller to avoid contention.

Keep in mind that with a 25MHz. external clock and the PLL bypassed at power-up, the write pulses are going to have to be timed with the internal I/O update interval, which appears to be 5.2usec intervals with the default count value of 40H.  My microcontroller can only write bytes at 2.2usec intervals, so four bytes cannot be written in the 5.2usec time interval, so the first thing I do is modify the update clock value to 80H in the first interval after RESET is brought low.  I only write two lower bytes then wait for the internal clock.   The interval changes to 10.4usec.  One question is do I have to write all bytes of a multi-byte register before the internal or external I/O update signal strobes?  It seems like I'm getting away with two bytes on the update clock register.

Following that is the write to the four control register bytes with the internal I/O update bit disabled.  Initially the PLL was being enabled with a multiplier of 12 decimal.  Problems encountered also made me leave the PLL disabled until later.  After the next internal update pulse the internal pulses stop.  There are no more afterwards.  Some 10usec later I reconfigure the port pin for the I/O update as an output port after setting the output value to logic low.  I then pulse the output to drive the I/O update line high, and apparently there is contention because the line will not go above two Volts.  Apparently the internal update clock generator was switched off, but the DDS is still driving the I/O update pin.  What is needed to get the internal driver released?

The third question: Do all four bytes of the control register have to be written?  Can I just write the one byte at address 1F and avoid modifying the update clock interval?  It seems as if there is an implied protocol, but I can find no documentation as such.