AD9957 spectral invert

AD9957 works in QDUC mode with 5 MHz modulation rate.

CFR1 = 00 20 00 02

CFR2 = 00 40 E8 00

CFR3 = 35 38 C1 28

PROF0 = C9 FA 00 00 1C 2F 83 7B

Input frequency (clk) = 50 MHz

Output frequency = 110.1 MHz

Pins 52, 53, 54 are electrically grounded (PROF0).

I[17:0] = sin(10 kHz)

Q[17:0] = cos(10kHz)

This type of modulation means that we shift radiofrequency to 10 kHz.

The problem is in sign of shifting during initialize of AD9957. I mean sometimes output frequency is 110.11 MHz and sometimes 110.09.

It happens if swap I and Q. Also it's possible to change output frequency by inverting Spectral Invert bit in Profile register.

Any ideas why DDS invert spectrum randomly after initialize?


  • 0
    •  Analog Employees 
    on Sep 1, 2011 5:10 PM

    This mode of behavior usually means there is a timing issue involving TxENABLE and its relationship to PDCLK and the data at the Parallel Data Port. It is absolutely critical that "I" data be present (and settled) on the parallel bus before the appropriate edge of TxENABLE (rising edge according to the register values you provided).

    The rising edge of TxENABLE causes the data assembler to treat the data captured by the next appropriate edge of PDCLK (rising edge per your register values) as "I" data. Per your register settings, PDCLK is set for 1/2 rate operation, so you get one rising edge per I/Q pair. You need to make sure the rising edge of TxENABLE occurs prior to the rising edge of PDCLK in order to guarantee proper phasing of the I/Q data pairs. Be aware, however, that PDCLK still operates at full rate internally. So if TxENABLE occurs too early, the data assembler could accept the internal PDCLK edge associated with your "Q" data as the starting point. If so, you will see a spectral inversion at the output.

  • In my device TXENABLE is connected to +3.3V.

    In datasheet also says about PDCLK wich is set for 1/2 rate operation: "...When this bit is set, the PDCLK rate is reduced by a factor of two. This causes rising edges on PDCLK to latch incoming I-words and falling edges to latch incoming Q-words.".

    In a next release of PCB I'll correct this mistake. But now I'm trying to find another way of syncronization.

    Thanks for your answer!

  • 0
    •  Analog Employees 
    on Apr 29, 2019 10:37 AM
    This question has been closed by the EZ team and is assumed answered.