AD9957 multichip sync

I've got three AD9957 on my board. They are clocked from AD9520. Clock is 50 MHz. I made such topology of PCB as length of trace CLK1 is equal to length SyncIn1, CLK2 equal to SyncIn2 and so on. Placement of IC's as on attached picture. Difference of CLK2 - CLK1 = CLK3 - CLK2 = 40 mm. All DDS in QDUC mode. In this mode I see 1.25 MHz on all SyncIn signals. Empeically I found the mean of Sync Receiver Delay = 7 when the SYNC_SMP_ERR pin is in false on the master's DDS. But neither this nor any other values of MultiChip register for slave DDS didn't have success. How should I calculate values of this registers? Or my PCB is wrong?

Thanks.

  • 0
    •  Analog Employees 
    on Sep 7, 2011 8:39 PM

    The first step to synchronizing multiple AD9957s is to ensure coincident REFCLK input edges. This is best accomplished by using a common clock source. In your case, using edge aligned outputs of the AD9520 should satisfy that requirement. However, you must also ensure equal trace lengths from the clock source to each AD9957 REFCLK input (in your case, this means the length of CLK1=CLK2=CLK3). Furthermore, if you are using the system clock PLL feature of the AD9957, make sure that all devices indicate a lock condition before you start the process of synchronizing devices. Having met the above requirements, the application of a synchronous reset pulse to all AD9957s should ensure that all of them are operating on the same internal system clock edge.

    The second step in synchronizing multiple AD9957s is to ensure that all of them have a coincident SYNC_CLK output. Assuming the first step has been satisfied, the second step is accomplished by providing synchronous SYNC_IN edges to all AD9957s. In your case, using the ADCLK846 is a good way to go. However, you should also make the SYNC_IN traces of equal length (that is, equal to each other, but not necessarily equal to the corresponding CLK trace per your diagram). Equal SYNC_IN trace lengths will ensure coincident edge arrival times at each of the AD9957 SYNC_IN pins.

    Now all that is left to do is to make sure the synchronous SYNC_IN signal at all AD9957s results in a simultanous internal "sync pulse" across all devices. This will cause the SYNC_CLK output signal from all of the AD9957s to be in lock step. The problem is that there is no way to guarantee an optimal relationship between each AD9957s SYNC_IN signal and its internal system clock edge because you have no way to view the internal system clock. For example, it is possible that the SYNC_IN edge occurs at exactly the same time as the internal system clock edge, which might create a metastable condition in the latches that control synchronization. This would render the synchronization circuitry useless. Clearly, we need to make sure the edge timing of SYNC_IN relative to the internal system clock edge meets internal setup and hold timing requirements.

    This is where a calibration procedure comes in. You must ensure that the SYNC_IN edge occurs at the proper time relative to the "invisible" internal system clock edge. To do this, you use the AD9957's "Sync Timing Validation Disable" bit (CFR2<5>) in conjunction with the SYNC_SMP_ERR output pin, as follows:

    1) Set the Sync Validation Delay = 0.

    2) Set the Receiver Delay = 0.

    3) Perform several sync validation measurements. That is, program CFR2<5> to a 1 then a 0 and record the state of SYNC_SMP_ERR.

    4) Increment the Receiver Delay value by 1 and repeat step 3).

    5) Repeat steps 3) & 4) until Receiver Delay = 31.

    NOTE: It is important to perform step 3) several times because the SYNC_SMP_ERR result is subject to metastable conditions if the internal system clock and SYNC_IN edges are not favorably related. So, you must take several measurements to ensure you are seeing a stable result rather than a metastable result.

    Once you build up a table of results (Receiver Delay vs. SYNC_SMP_ERR) you should have results with a pattern similar to those below, where Sync_Smp_Err = X means intermittent 0/1 results (indicating a metastable condition).

    Receiver Delay SYNC_SMP_ERR
    0 0
    1 0
    2 0
    3 0
    4 X
    5 X
    6 0
    7 0
    8 0
    9 0
    10 0
    11 X
    12 X
    13 0
    14 0
    15 0
    16 0
    17 0
    18 0
    19 0
    20 X
    21 X
    22 X
    23 0
    24 0
    25 0
    26 0
    27 0
    28 X
    29 X
    30 0
    31 0

    Results like those above indicate the most robust Receiver Delay values are at about 8, 16 and 25. That is, the midway point within groups of SYNC_SMP_ERR = 0. Typically, you will want to choose the Receiver Delay value associated with the middle of the first group of 0's surrounded by X's (8 in this example).

    Be aware that different clock frequencies and different choices for the Sync Validation Delay value will usually result in measurements that do not exactly match the example above. However, the pattern of results should remain intact. That is, SYNC_SMP_ERR yielding groups of 0's with intervening groups of X's.

    Once this calibration process has been performed on each AD9957 all of the devices should be synchronized. Furthermore, to ensure that all devices have the same PDCLK timing, be sure to use the same "Sync State Preset Value" across all AD9957s. You should be able to validate synchronization by observing the SYNC_CLK output of the AD9957s. They should all be in lock step.

    Message was edited by: Ken Gentile

    Correction: Changed "Sync Validation Delay" to "Reciever Delay" in the 3rd sentence of the 1st paragraph following the table.

  • 1. Master DDS works fine.

    RecDelay SYNC_SMP_ERR
    0 0
    1 1
    2 1
    3 1
    4 0
    5 0
    6 0
    7 0
    8 0
    9 0
    10 0
    11 0
    12 0
    13 1
    14 1
    15 1
    16 0
    17 0
    18 0
    19 0
    20 0
    21 0
    22 0
    23 0
    24 0
    25 1
    26 1
    27 1
    28 0
    29 0
    30 0
    31 0

    2. Slave devices have SYNC_SMP_ERR = 1 all the time. All fields of Multichip Sync Register are 0 except Sync Receiver Enable, Sync Generator Enable and Sync Receiver Delay.

    3. My board doesn't have equal trace length for REFCLK and for SYNC_IN pins. But the difference between REFCLK and SYNC_IN pin are the same for all channels. I mean the first slave device is placed for 40 mm far from the master device. The second slave is 80 mm. And the length of REFCLK and SYNC_IN for every next channel increased for 40 mm. It means that edges REFCLK and SYNC_IN are delayed for the same value. Delays measured by waveRunner 64Xi oscilloscope:

    Channel SYNC_IN, ns REFCLK, ns REFCLK - SYNC_IN, ns
    1 (Master) 2,57 6,22 3,65
    2 2,84 6,44 3,6
    3 3,11 6,78 3,67
    4 3,39 7,09 3,7

    Reference point for measure is SYNC_OUT pin of master DDS. I.e. 2.57 ns is delay between SYNC_OUT and SYNC_IN of master channel (delay of ADCLK846 + traces); 6.22 ns is delay between SYNC_OUT and REFCLK of master DDS. As you can see the edge delay between REFCLK and SYNC_IN for the second channel is decreased only for 50 ps. For the third channel increased for 20 ps. I guess that this delays are not significant.

    Also I tried to measure delay between SYNC_OUT and SYNC_CLK but on the slave devices it's impossible because internal logic of DDS makes signal (250 MHz) on this pin unstable while Sync Receiver Enable = 1.

    Why aren't the slave DDSs syncronized? Are there any other reasons except edge align?

  • 0
    •  Analog Employees 
    on Sep 8, 2011 6:33 PM

    It is not possible to synchronize multiple AD9957s without first ensuring edge alignment of the REFCLK input across all devices (see Fig. 59 in the datasheet). Edge alignment of the REFCLK is a requirement for synchronization. It is the only way to ensure the internal system clock of all devices are time aligned.

    The best way to guarantee edge alignment at the REFCLK input is to use a common clock source and run traces of equal length to each REFCLK input. Your use of the AD9520 to distribute the REFCLK should qualify as a "common clock source". However, you must also ensure coincident edges at all REFCLK inputs. You can do this with equal trace lengths or by controlling the edge timing at each source to provide coincident arrival times at each REFCLK input.

    The next requirement is edge alignment at the SYNC_IN input across all devices (see Fig. 59 in the datasheet). Again, the simplest way to guarantee this requirement is to run equal trace lengths from the output of the device that distributes the SYNC_OUT signal from the master AD9957 to the SYNC_IN of all AD9957s (including the master). Unlike the REFCLK input, however, you have a some margin on the SYNC_IN signal because the Sync Recv'r allows you to add internal delay. However, the delay difference between your longest and shortest trace must be within the total adjustment range of the Sync Recv'r (which tends to run in the 2.5 to 3 ps range).

    Although I did not mention this before, you should also try to make the RESET and I/O UPDATE signal edges coincident across all devices, as well.

  • Hi Ken,

    I apologize for resurrecting an old post, but your write up has helped me understand multichip sync a lot.  I'm attempting to sync two AD9957's in much the same way as the original poster, and I have a question about the algorithm you posted here.  Why do you set Sync_Validation_Delay (SVD) to 0?  According to the AD9957 Datasheet, page 43, SVD should be some non-zero value that's a fraction of the SYSCLK period.  It gives an example of 300ps for a 1GHz clock.  Could you please elaborate?

    Thanks!

  • 0
    •  Analog Employees 
    on Dec 12, 2016 6:45 PM

    Setting SVD to 0 selects the minimum delay, which is not to say "zero" delay. The algorithm effectively calls for running the "sync validation test" over the full range of SVD values and then analyzing the results afterward. If all goes well, you should be able to see clear regions of pass/fail values. Select a final SVD value that falls in the middle of one of the "pass" regions.