I've got three AD9957 on my board. They are clocked from AD9520. Clock is 50 MHz. I made such topology of PCB as length of trace CLK1 is equal to length SyncIn1, CLK2 equal to SyncIn2 and so on. Placement of IC's as on attached picture. Difference of CLK2 - CLK1 = CLK3 - CLK2 = 40 mm. All DDS in QDUC mode. In this mode I see 1.25 MHz on all SyncIn signals. Empeically I found the mean of Sync Receiver Delay = 7 when the SYNC_SMP_ERR pin is in false on the master's DDS. But neither this nor any other values of MultiChip register for slave DDS didn't have success. How should I calculate values of this registers? Or my PCB is wrong?