AD9833-CLK function

Hello,

I am using ad9833 in migration product for my new project ,the history of this product is earlier ML2036  was used, now this IC gets obolate so we are selecting ad9833.

Now the main differance is,in ML 2036 there are 2 registor (shift and latch)  1st data will loaded in shift registor and then latching registor gets upadted  and hence new word is loaded in ML2036,in ad9833 there is no such regisotr available

Second differance is in ML2036 data  gets loaded on rising edge which is exactly reverse as per ad9833.

So my problem is this all activity is hard codeded in FPGA and we are avoiding any change inside FPGA so kindly do quick look and suggest me that is there any ic availble in Analog device or i have to go for some differance solution ?

Imtiyaz

Parents
  • Hi, Imtiyaz,

        Interestingly, in spite of the difference in description between the ML2036 & AD9833, the serial programming waveforms are very similar between the two products (ML2036 datasheet, p7 & AD9833, p3), when FSYNC on the AD9833 is used for LATI on the ML2036.  Even though not specifically described, the AD9833 does have a separate input serial register to hold the serial data before transferring to the frequency control hardware, as is done on the ML2036, and the actual latching occurs when FSYNC goes HIGH.  The trouble comes in the fact that for the AD9833, SCLK must stay HIGH while FSYNC goes LOW (datasheet, p. 9, under Serial Interface), while the opposite is true for the ML2036 (datasheet, p. 8, under Serial Digital Interface).

        What are the timing for the SCLK and LATI from the FPGA?  A one-shot plus OR an gate may be needed to keep SCLK HIGH for the ADL9833, if not taken care of by the FPGA.

        An additional word of caution: ML2036 requires a single 16-bit serial data stream to be transmitted LSB first, while the AD9833 requires three 16-bit streams, MSB first, to complete a frequency change.  These, hopefully, will be correctly handled in software.

         Hope this helps.

    Benjamin

Reply
  • Hi, Imtiyaz,

        Interestingly, in spite of the difference in description between the ML2036 & AD9833, the serial programming waveforms are very similar between the two products (ML2036 datasheet, p7 & AD9833, p3), when FSYNC on the AD9833 is used for LATI on the ML2036.  Even though not specifically described, the AD9833 does have a separate input serial register to hold the serial data before transferring to the frequency control hardware, as is done on the ML2036, and the actual latching occurs when FSYNC goes HIGH.  The trouble comes in the fact that for the AD9833, SCLK must stay HIGH while FSYNC goes LOW (datasheet, p. 9, under Serial Interface), while the opposite is true for the ML2036 (datasheet, p. 8, under Serial Digital Interface).

        What are the timing for the SCLK and LATI from the FPGA?  A one-shot plus OR an gate may be needed to keep SCLK HIGH for the ADL9833, if not taken care of by the FPGA.

        An additional word of caution: ML2036 requires a single 16-bit serial data stream to be transmitted LSB first, while the AD9833 requires three 16-bit streams, MSB first, to complete a frequency change.  These, hopefully, will be correctly handled in software.

         Hope this helps.

    Benjamin

Children
No Data