AD9952: Exact functionality of Sync_in pin?

Hello,

I had a question about the AD9952 and possibly other DDSs. I am using this DDS with the PLL at 16x. I know the resulting system clock is divided by 4 again to yield the sync_clock.

So my clocks are: sys_clk = 4 * sync_clk = 16 * ref_clk.

Now, I would like the sync_clk edges to line up with those of the reference clock, or at least have a fixed relation to it. I would like to use automatic synchronization mode for this. However, I have no 'master' DDS or any other way to generate a 'master' sync_clk.

So what exactly is the functionality of the sync input in 'automatic synchronization' mode?

What logic is behind it? Is it edge sensitive (i.e. does it line up two edges?)

Can I feed my reference clk or some simple derivative thereof into this pin to get the edges lined up?

Thanks,

Dirk-Jan

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    •  Analog Employees 
    on Aug 2, 2018 4:32 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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    EZ Admin
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    •  Analog Employees 
    on Aug 2, 2018 4:32 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
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