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On page 5 of the AD9912 datasheet, under "SYSTEM CLOCK INPUT/SYSCLK PLL Bypassed/Input Resistance" the range is specified as 2.4 to 2.9 kohms differential.  But on page 21, Figure 47 the schematic for "SYSCLK BYPASSES" shows a 500 ohm resistor to RF ground at each of the SYSCLK inputs.  That would result in 1.0 kohm differential input resistance instead of the 2.4 to 2.9 kohms specified in the table on page 5.  What am I missing?  Thanks.  Steve

  • I'm not sure which one is right. The designer would have respond to this contradition or oversight. However does this help?  Whether its 1k or 2k differentially, that in parallel will an external 50ohms close to the REF CLK pins is roughly an equilvalent 50ohm load regardless of 1k or 2k as far as a REF CLK source is concerned. This is done on the AD9912 evaluation board.

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