I have a question about the 9914/15 chips - if the PLL if not used, can the PLL pins be left floating ?
Also, is it safe to tie the profile, F0/3 mode pins and everything else that should have a static logic level directly to ground or 3.3 DVDD or resistors should be used? Can the logical "1" pins be left unconnected?
When PLL's are not in used, it is safe to let it hanging. The PLL is followed by a multiplexer which selects either the PLL or a direct path. The evaluation boards are implemented with headers and the high logic should be tied with DVDD and it may be tied directly. More information can be found on the datasheet, the PLL is on page 21.
The AD9914 function pins (28,29,30,31) and all the parallel port pins (32 pins) all have internal pull down ~30k ohm resistors. So, these pins should go to a logic 0 state if not driven or tied off. All other CMOS inputs do not have internal pull down resistors. So, if the feature or circuits that these pins are used is enabled, these pins should not float. For example, the master reset pin, profiles pins, IO_UPDATE pin etc do not have internal pull down resistors.