AD9957 evaluation board


I'm using the AD9957 evaluation board and software and modulating at 40MHz and using the multiplier (x25) to obtain a 1GHz clock in QDUC mode. Also, we designed our PLL loop filter from the tool provided and populated the board. For the most part, we see what we expected from the simulations, however there are a few questions I was hoping to get answered:

  1. We seem to lose the PLL in quadrature modulating mode, the light on the software control window blinks. This doesn't happen in singletone mode. As far as I understand from the data sheets these modes shouldn't affect that, so why is it losing the PLL lock in quadrature mode?
  2. Is it normal to see spurs on the spectrum analyzer every 25MHz (clock frequency) from the center frequency? I attached a picture of this phenomenon.
  3. What is PFD and Antibacklash PW? The data sheet and user guild seemed to skip what those are, but they're on the Control view window for the evaluation software. How do these affect the performance?

Thanks in advance for any assistance you are able to provide.
  • 0
    •  Analog Employees 
    on Aug 14, 2012 4:43 PM

    Based on the spectrum analyzer plot, can I assume your first sentence has a typo and that you are modulating at 400MHz as opposed to 40MHz? Also, I gather your reference clock is 40MHz with 25x translation to 1GHz.

    1. You are correct in assuming a disconnect between QDUC mode and the system clock PLL. They should not affect each other. However, if any signals on the board are coupling into the PLL via the loop filter circuit, then the PLL could possibly be pushed out of lock. I mention this because in single tone mode the only signal of significance is the DDS output, which is not likely to interfere with the PLL circuitry. In QDUC mode, however, you have the addition of the baseband signals (I, Q, TxEnbl, etc.). I assume these originate from an external circuit and are tied into the evaluation board. Hence, the potential for some unwanted coupling.

    2. At present I don't have a good explanation for the spurious signals at 25MHz offset from the carrier. I assume the DDS is set to generate a 400MHz carrier. What about the baseband signals? Can you provide some detail regarding the I/Q input signals?

    3. The PFD and anti-backlash settings are best left alone. In fact, their appearance in the software is probably an oversight. These are test bits used for debugging the original silicon.

  • Sorry about the confusion. I am modulating 400 MHz and the reference clock is 40MHz with 25x translation to 1GHz.

    1. We are not using an external circuit. The I and Q data streams are loaded through the evaluation software using the on-board fifo. Could clocking the data at 20 MHz have an effect?

    2. Our I/Q input is 1 gbps oversampled by 10. I'll attach the .fifo that was used.

  • 0
    •  Analog Employees 
    on Aug 15, 2012 4:52 PM

    I did not realize you were using the onboard FIFO. That changes the picture completely. The FIFO circuit delivers data in burst mode. That is, the FIFO loops through its contents with a pause between each loop. In your particular case, 28K of I/Q pairs are transmitted, then there is a pause, then they are retransmitted, etc. This can definitely create unusual spectra. It's very possible the +/-25MHz spurious is a FIFO artifact.

    What is the interpolation factor of the CCI filter in the active profile during modulation?

    By the way, I noticed there is clipping in your FIFO data set. Is this intentional?

  • That is very interesting. We are now looking into loading the fifo data into the on-board RAM.

    The CCI interpolation rate is set to 25.

    I don't believe the clipping is intentional. We were scaling to +/- 1 in 18 bit 2's comp.

    I'm attaching a document that details how the clocking was calculated.

  • 0
    •  Analog Employees 
    on Aug 16, 2012 4:52 PM

    The "clocking" document was clear and concise and answers all my questions.

    Using the RAM will help because it allows you to loop through the data sequence without a pause between iterations. However, the RAM is only 1024 samples deep. So you will only be able to loop through 100 symbols (assuming 10 samples per symbol for pulse shaping). Furthermore, using the RAM limits the I/Q data to 16-bit resolution resulting in reduced spectral performance relative to driving the parallel port directly.

    In spite of the drawbacks to using the RAM, you should still be able to get a reasonably good representation of the AD9957's modulation capability.