AD9958: No output

Question

Hello 
 I have developed a board using the AD9958 and it's not working properly. The DDS is controlled by a ATmega on a Arduino board. 
 I have attached the schematics. 
 The communication via SPI works, but there is no output on both channels. First I want to run the DDS in single tone mode. 
 For initialising I send over SPI following. 
 CSR set to 0xC2 
 FR1 set to 0xD050A0 (>255MHz, PLLx20, CP 75µA, Single Tone Mode.) 
 CFTW0 set to 0x0083126E (1 MHz) 
 IO_Update 
 After that I read all registers. CSR and FR1 are correct but CFTW0 is 0x00000000. If I select only one channel CFTW0 is read correctly. But there is no frequency on the outputs on both constellations. 
 I tested Sync_CLK (FR1 0xd05080) and there is an output with 125MHz. 
 I'll appreciate any hint for the troubleshooting of the problem. 
 Thanks, 
 Roman Ritter

stgtroman · Accepted Answer

Hello, 
 the error in my schematics with the resistance and the capacitor on the loop filter pin follows from an error in the data sheet for the AD9958 evaluation board. 
 http://www.analog.com/static/imported-files/eval_boards/57241686299254AD995EB_0.pdf 
 There it is described incorrectly. 
 After correcting this error I have found an error in communication. In the first thread I've set FR1 to 0xD050A0. Unfortunately, I have disabled thus also the Ref Clock Curcuit. 
 Probably I have not tested the output, when FR1 was written correctly and I measured the 125MHz at SYNC_CLK. 
 Now all works correctly. 
 Thank you all for your help. 
 Regards, 
 Roman)

ADIApproved · Answer

Hello, 
 In read back mode, you must enable (using the channel enable bits in CSR) only the channel you're trying to read back. So, the other channel enable bits must be logic 0 in read back mode. That said, it sounds like it is working correctly if that is done, correct? 
 Note: In your schematic you have the PLL loop filter referenced to ground. It should be referenced to 
 1.8V. This may degrade ac performance. Also, I would recommned changing the 680 ohm resistor for the PLL 
 loop filter to 0 Ohms. We actually build the evaluation board with 0 ohms and 680pf, not 680 ohms. 
 The fact that you using the PLL and you have a SYNC_CLK running at 125MHz sounds like your code is OK. 
 Double check the output. I would isolate the transformer from the output and then check across the output 50 termination resistors to AVDD for a signal.

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AD9958: No output