100Hz to 1.25MHz signal generation with AD9952

Hi

we are in prototyping and test stage with an larger design hat involves over 30 ADI IC's (over 20 different ones!) - one part of the design is sinus signal generation with single frequency range span of 100Hz to 1.25MHz (output +-10V single ended, capacitive load drive up to 10nF) , for this task we use:

AD9952 followed by two stages of differential low pass filters (cut off frequency 1MHz) implemented with AD8132, followed by: AD8251 doing differential to single ended conversion and applying gain of 1,2,4 or 8 (8 being used mostly), followed by AD5543 which applies Gain adjustment followed by ADA4004 performing I to V conversion and adding Offset generated by AD5422

AD9952 is clocked from master clock circuit implemented with AD9912 (1GHz clock from 25MHz crystal) designed to generate clock in the frequency range of 40..80MHz (divided by 2 later for ADC clock). AD9952 is used in PLL bypass mode as the complete system must be able todo instant changes to the the frequency (both for AD9952 used as per channel signal as to the AD9912 generating master clock). AD9912 has Microcircuits LFCN-80 low pass filters in the feedback path in series with capacitors. AD9912 output is used as clock to AD9952 directly (with DC block capacitors), final design will use AD9512 clock distribution IC to send the master clock or master clock/2 to all channels and FPGA.

To our pleasant surprise the complete system did start to work almost instantly as designed, as soon as we wrote some C code to initialize the programmable devices used, we got output signal!

Now question(s):

Having AD9952 clocked at near 80 MHz (78MHz to be exact) and generating 1MHz output signal we see DDS DH2 spur at about -58dB, never better if we look at AD9952 datasheet, then results at about -70dB should be possible, but no matter we do, we have not seen second harmonic (DH2 ?) below 60dB. Is this normal or do we have some design error?

What makes us worry a bit is the fact that we measured about same value for DH2 when using AD9952 output directly to AD8251, as when using the two stages low pass filter, the measurement was about the same, but for 1MHz fundamental signal our low pass should have filtered DH2 already. Of course for lower output signals the low pass will not filter DH2 or DH3 an more, so we really depend on the DDS output to be clean enough.

In our setup we use only SMA cables between functions blocks and Agilent DS090254A again connected directly to the signals (with resistor divider to adjust the voltage range). DH2 is measured with DSO FFT function. Measuring the signal with spectrum analyzer (Signalhound) did give about same results, DH2 was around -52dB (but we do not trust that much those reading as Signalhound is not that good instrument for low frequency measurements.

AD9912 derived clock is also used to drive AD7760 ADC converters, we hope that the clock generated has low enough jitter, but this is very hard to prove until we have actual measurements of the ADC. We are waiting for 0.3ppm THD sinus signal generator - signal analysis on good enough signal would be some sort of indication that the jitter is low enough. We do not have equipment to measure the jitter in sub 10pS range our DSO did show 14.5 pS RMS jitter. Well we do not trust that much this reading from DSO and the measurement was done on single HSTL output from AD9912 connected to DSO (via bypass capacitor of course). Sure for AD7760 clocking we must somewhere convert the differential clock to single ended again.

Our test system is currently made from 10 different "building blocks" so we can change some function block to be done using different IC or different schematic-values, so any help at this stage is valuable as we can still change the design.

Antti

  • 0
    •  Analog Employees 
    on Sep 10, 2012 5:16 PM

    Hello trioflex,

    I'm not that knowledgable about spurs and magnitudes so maybe someone else can help there, but there is one thing that confuses me.  Why are you using one DDS, namely the AD9912, as the reference clock for ADCs and another DDS?  Is it your application requires changing the sample frequency quickly?  If not then you might be better off with a PLL or a clock generator/distribution IC.

    Do you have a general block diagram or a schematic you can share?  Keep in mind this forum is open to the public so anything you share can be seen by anyone.  Also, did I understand correctly that you have multiple boards connected together via SMA cables instead of one PCB?

  • Hi Kevin,

    the project (single PCB at the end) looked so complex that we did not want to make ONE SHOT to get it all right (final board is 12 layer one), so in order to test all functions, we developed small functions block, mostly with one main IC. One such block is AD9912 based clock generator. In order to TEST those blocks and modules we have USB powered "mother units" that have SMA cables for the analog and clock signals.

    Now, we DO NOT WANT USE AD9912!! We really would love to NOT USE IT. But our client spec says:

    1. Range: 20MHz-40MHz (we actually plan to use 40..80MHz and divide by 2 with AD9512)
    2. Resolution: less 1 Hz
    3. Frequency Update rate: 1ms maximum (>= 1000 changes of frequency per second)
    4. phase-continuous frequency tuning
    5. Clock for AD7760 SFDR <= 130dB in 10KHz..1MHz range (except harmonics)

    Now we really do not know any way of doing first 4 requirements without DDS. PLL can probably lock fast enough, but what is output frequency when the PLL is not locked ??

    Requirement 5 is pretty scary also, specially because of the jitter requirements... and large frequency range of the clock required. We use 80MHz low pass filters with AD9912, so I bet when AD9912 output is near 40MHz jitter is larger than at frequencies closer to the filter cut off.

    Any advice?

    /Antti

    PS we would appreciate offline ADI support in this case, if possible. It is really TO EDGE project with almost only ADI ICs utilized!

  • 0
    •  Analog Employees 
    on Sep 11, 2012 9:48 PM

    The 2nd harmonic distortion of -58dbc sounds excessive gvien the conditions above.  Are you measuring this at the AD9952 output? If so,  I would suspect a output compliance issue or termination issue. Can you elaborate on the exact configuration of the AD9952 output. Also, include the DAC full scale current setting. Have you isolated the DDS output from the other devices and measured the same distortion?

  • Hi

    what made us a bit wonder was that we measured about the same level of 2nd harmonics DIRECTLY at DDS output as well as after two stages of differential active low pass filters! The 2nd harmonic was well in the low-pass stop-band, but DSO FFT measurements did not show any attenuation of the harmonics at all.

    We will be doing more measurements next week, this time we hope to use our own AD7760 based product to measure the DDS output. We are not yet satisfied with the AD7760, in our setup we are seeing also somewhat too much harmonics: we measure a 1KHZ signal source that is claimed to have 0.3 ppm THD our AD7760 board however is giving THD readings only somewhat 8 ppm.

    But we believe AD7760 is already way superior as measurement device compared to the 20GS/s DSO from Agilent that we have tried to use so far.

    Screenshot from 1KHz reference sinus with AD7760 at 625KSPS with default filter. We hope that we see less than 58dB for the DDS using this ADC as signal capture unit. In the screenshot above the small spike at -184 dB is TRACO dc-dc converter running at 300khz

    We have not yet measured AD9952 output with AD7760 but we are very excited already!

    In our DDS measurements we had setup with ONLY DDS IC on special test PCB, with almost direct connection to SMA connectors and then to the measurement system. Later the low pass filter board was connected, by using 2 SMA-SMA cables (differential filter).

    If we do not get better results next week, I can give more information about the schematic and setup we use.

    /Antti

  • Hi

    we are now measuring AD9952 output with AD7760, the spectrum is bit cleaner but we have not seen better that 76dB SNR yet..

    Setup: AD9912 generating 80MHz, filtered with microcircuits LFCN-80 80MHz low pass, CMOS divider set to 2, CMOS output clocking AD7760, HSTL outputs clocking AD9952 (80mhz). AD9952 is set PLL bypass, generating 1KHz, AD9952 signal is sent to differential active lowpass with 1MHz cutoff, this signal is sent to AD4940 that does single do differential conversion and then measured with AD7760 with 625K ODR.

    We when we bypassed low pass filter and connected AD9952 diff outputs directly to AD4940 differential inputs we did see about same SNR number (but way more harmonics).

    So, what else to check? I assume we should be able to get more than 80dB SNR out of AD9952?