AD9957 PLL

Hi

         i am using 20 MHz external CLK for AD9957 PLL input, but it is not locking  for frequency 800 MHz.it gives a 20-30 MHz wide signal at pin no 55.  centered around 320 MHz.(pll loop filter BW=2.5 MHz,VCO=4)when i change the  VCO from 4 to 5,it results increase in current & same spectrum shifted to around 400 MHz,pl suggest why PLL is not locking.

its ref clk circuit is working by verifying /8 output frequency & /4 output at pin no 55.

one more observation when loop filter is designed for 50 KHz ,the devices does not draw current.

  • 0
    •  Analog Employees 
    on Oct 12, 2012 6:42 PM

    Are you using the AD9957 evaluation board or not? If so, the evaluation board does not populate the PLL loop filter components. I have attached an excel file to help calculate the values for the desired conditions. Note, 50Khz loop bandwidth is probably too narrow. The internal VCO in the AD9957 is a ring oscillator type. The close in phase noise of this type vs LC is typically higher. So, if you have a REF CLK source with good in close phase noise performance, I would suggest running the loop bandwidth around 1Mhz verses 50KHz. That should improve the overall close in phase noise performance.

    attachment.xls