What is the minimum pulse width of the SYNCIO signal in order to reset the serial interface communication?
Does CS need to be asserted (low) for SYNCIO to have effect? (would be natural, but the information is missing from the DS).
If IO_UPDATE setup and hold times are not followed (i.e. if the signal is controlled by a simple I/O pin of a microcontroller), what would happen? Assuming a meta-stable flop inside the chip, but what would be the effect?
Assuming the exact timing of the register update is not important, is there a way to avoid an external flip-flop to synchronize the IO_UPDATE signal, when driving the signal from a simple microcontroller (on another clock)?
The SYNCIO minimum pulse width was not characterized. It is an asynchronous input and I would think the minimum SYNCIO would be no more that one SCLK period. The CSB line does not have to be asserted logic low for SYNCIO to take affect. IO_UPDATE can be sent asynchronous, the trade off is propagation time uncertainty.
Thanks a lot.
I am however uncomfortable with the notion of "sending" I/O_UPDATE. This type of wording is also used in the DS and confuses me. I/O_UPDATE refers to the pin - you can set the pin high or low. But you can't "send" it. My recommendation would be to tighten up the wording around this throughout the DS.
Most places in the DS it looks like "I/O update" refers to something that can be sent - but it is not defined anywhere. Maybe some internal thing to the chip?. Whereas "I/O_UPDATE" refers to the pin.