AD9951 Timing and SFDR

First thanks to AD for providing this forum.

The specific device (at this time) that I am concerned about is the AD 9951 DDS. I have been using it for some time in a DDS and a couple of issues come to mind:

1. In the data sheet (timing characteristics) it is stated that the I/O Update signal has a required set-up time with respect to the Sync_Clk, and I notice that at least one of the AD evaluation boards has the possibility to use the Sync_Clk to re-time an asynchronous I/O Update signal. Is this only relevant if you are using several AD9951's and want them all to behave in a common way, or is it necessary in any case ? When using a single chip, what's the consequence of not ensuring the needed set-up time ? Delayed update due to some "metastable" state in an internal register ? Complete  corruption of the dataset ? or nothing ? (I have noticed that virtually all applications I have found do not re-clock the I/O update signal, nor do I at present, and it seems to work pretty reliably).

2. The wideband SFDR for a AD9951 with a 400 MHz clock and outputting a frequency in the range of 40 to 80 MHz is quoted as 62 dbc. I am clocking an AD9951 at 116 MHz (lo-phase noise crystal oscillator) and the output frequencies I am using are in the range 19 to 21 MHz. The wideband SFDR seems to be in the range of 40 to 45 dbc. I am not looking at the harmonics, but the signals produced in the range of 0 to 35 MHz. The higher order signals are filtered out. Spectrum analyser trace with 19.001500 output frequency attached.

Any comments ?

(As far as I am aware the chip is properly grounded, including the backside pad and this is probably born out by the low narrowband SFDR). I have seen several other users of the AD9951 show spectrum analyser plots where the clock is 400 MHz, but the wideband SFDR in a 50 MHz bandwidth with outputs in the range of 23 MHz is still showing as about 45 dbc. It seems that the AD9912 is about the best choice if one wants about 60 dbc SFDR. Again any comments ?

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