I have some questions connected to the PLL and the CML on the AD9956 evaluation board (including a VCO at ~2450MHz). I am using the eval board as a fractional divider loop as stated in the data sheet, i.e. the VCO output is fed into the DDS/DAC and compared to a reference signal (not the on board crystal) connected to the PLLREF input (25MHz). The R-divider output is fed into the CML driver to generate a clock signal.
1. For reference, the PLL LOCK/SYNC pin should indicate whether the PLL is locked to the ref. signal (locked at logic 1). However, I observe the pin to be high, in case the loop is locked but also if the charge pump is at the edge of its range (0V or 3.3V) and the loop cannot work anymore. What exactly does the IC test to decide if the PLL is working or not?
2. The CML driver is equiped with two outputs. Using this driver, I want to feed the REF_IN of an AD9959. This input is single ended, so I am not quite sure how to connect these boards properly, I expect at least some modifications, because the CML output is supposed to be terminated with 100Ohms for proper PECL mode. Any hints here are welcome!
3. Eventually, I need the AD9956 to have a clock signal output at 500MHz. Therefore, the VCO need to be changed (one at 500MHz seems to be reasonable). Can you give any hints, how to design the loop filter?
When CFR2<24> is set to 0 (default) and PLL_LOCK is a status indicator the response is as follows. A constant high level (3.3V) on this output indicates that the loop is unlocked. There will be no pulses when the loop is significantly out of lock. "Significantly out of lock" means that the input edges to the PFD are on a cycle by cycle basis always greater than approximately 0.5ns apart. A constant low level (0v) indicates that the edges are aligned closer than approximately 0.5ns and remain so on a cycle by cycle basis. This is a locked state. Some pulsing may be observed during the locking process whenever on a cycle by cycle basis the separation toggles between being within ~0.5ns to being outside of ~0.5ns. The loop is not locked at this point. There are just samples during the phase slipping process where the edges are aligned for that cycle. Also, we must state that there is a bug with this function. If there is no Reference input signal at all. The locking circuitry may not reset and will give a false lock indication.
As far the CML output of the AD9956 driving the AD9959 board, I would remove R47, if populated. Regardless, you should have plenty of voltage swing to drive the REF CLK inputs of the AD9959. There should be no dc issues because both CML output and AD9959 REF CLK inputs are ac coupled.