Porgrammable phase/amplitude dithering is listed in the AD9954 features on the front page of the datasheet, but nowhere in the datasheet is there a description of how to implement it, or what it does. Please provide some guidance.
The AD9954 DDS core includes optional phase and/or amplitude dithering controlled via the CFR1<20:16> bits. During characterization, we found there to be little impact when using this feature, so we chose not to promote it heavily, but neglected to strip it from the features of the part. That said, the feature still exists, and here is what you need to know to check it out yourself:
Phase dithering is the randomization of the state of the least significant bits of each phase word.
Phase dithering reduces spurious signal strength caused by phase truncation by spreading the spurious energy over the entire spectrum. The downside to dithering is a rise in the noise floor. Amplitude dithering is similar, except it affects the output signal routed to the DAC.
The AD9954 uses a 32-bit linear feedback shift register (LFSR), to generate the pseudo random binary sequence that is used for both phase and amplitude dither data. The LFSR will generate, at the dds_Clock rate, the pseudo random sequence only if dithering is enabled. The enable signal is the OR of the dithering control bits (CFR1<20:16>).
Phase dithering is independently controlled on the four least significant bits of the phase word routed to the angle rotation function. That is, any or all of the phase word four least significant bits may be dithered or not dithered, controlled by the user via the serial port. Specifically, the CFR1<19> bit controls the phase dithering enable function of the phase word <16> bit for all four phase dither instances. The CFR1<18> bit controls the phase dithering enable function of the phase word <15> bit for all four phase dither instances. The CFR1<17> bit controls the phase dithering enable function of the phase word <14> bit for all four phase dither instances. The CFR1<16> bit controls the phase dithering enable function of the phase word <13> bit for all four phase dither instances. This enable function is such that if the bit is high, dithering is enabled. If the bit is low, dithering is not enabled.
Amplitude dithering uses one control bit to enable or disable dithering on the output of all four angle rotation blocks.
If the amplitude dither enable bit (CFR1<20>) is logic 0, no amplitude dithering is enabled and the data from the DDS core is passed unchanged. When high, amplitude dithering is enabled.