PDCLK problem of EVAL-AD9957

Hi,

I'm working with the AD9957 which is controlled by a DSP(TMS320 F2812). QDUC mode is selected. I can send control words to AD9957 sucessfully, and the SYSCLK is right, but the PDCLK pin does output the frequency I want, and the PDCLK is enabled. Plus, the Single Tone mode is right, that is I can get the wanted output wave.

Thanks very much!

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  • Thanks for your reply!

    Yes, my PDCLK pin has no expected signal in QDUC mode. In my QDUC mode, the PDCLK pin is always logic low, despite the fact that the PDCLK enable bit has been set as logic high. My control words are as follows (I use the crystal resonator on the backside of the board, 25MHz):

    CFR1: 0x0000 0000;     //QDUC mode

    CFR2: 0x0040 0820;     //PDCLK is enabled

    CFR3: 0x1a1f 4130;      //multiplication factor is 24, then the SYSCLK = 24*25 = 600 MHz,

    Profile0: 0x3cb5 0000 2000 0000     //DDS output is 75MHz. CC Interpolation Rate is 15, so the PDCLK = 600/(2*15) = 20 MHz;

    Thanks!

Reply
  • Thanks for your reply!

    Yes, my PDCLK pin has no expected signal in QDUC mode. In my QDUC mode, the PDCLK pin is always logic low, despite the fact that the PDCLK enable bit has been set as logic high. My control words are as follows (I use the crystal resonator on the backside of the board, 25MHz):

    CFR1: 0x0000 0000;     //QDUC mode

    CFR2: 0x0040 0820;     //PDCLK is enabled

    CFR3: 0x1a1f 4130;      //multiplication factor is 24, then the SYSCLK = 24*25 = 600 MHz,

    Profile0: 0x3cb5 0000 2000 0000     //DDS output is 75MHz. CC Interpolation Rate is 15, so the PDCLK = 600/(2*15) = 20 MHz;

    Thanks!

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