PDCLK problem of EVAL-AD9957

Hi,

I'm working with the AD9957 which is controlled by a DSP(TMS320 F2812). QDUC mode is selected. I can send control words to AD9957 sucessfully, and the SYSCLK is right, but the PDCLK pin does output the frequency I want, and the PDCLK is enabled. Plus, the Single Tone mode is right, that is I can get the wanted output wave.

Thanks very much!

  • Hi,

    Do you mean the PDCLK pin does not output frequency? Your post is as follows:

    xubing wrote:

    but the PDCLK pin does output the frequency I want, and the PDCLK is enabled.

    The AD9957 has 3 basic operating modes:

    1. QDUC mode (default)
    2. Interpolating DAC mode
    3. Single Tone mode

    At Single Tone mode, since the parallel data control is disabled, you would expect to have no output frequency at PDCLK pin.

    In your case, if you are in QDUC mode, there should be a signal available at the PDCLK pin (given PDCLK enable bit is logic high).

  • Have you populated the loop filter components in the board?

    The board is not populated with the components for loop filter. It is needed if you will use the internal PLL. A PLL loop filter tool can be downloaded in the evaluation board page of AD9957.

  • No, the short of gnd (pin 2) and vcc (pin 4) has nothing to do w/ the PDCLK problem. Although the shorting may affect device reliability (if shorting is remained after a longer period of time), but since, you have also tested the board in QDUC mode using the eval software and PDCLK pin had the correct signal, then that shows the part is working.

    So here is worth checking on the set-up:

    1. Please check if the XTAL_SEL has 1.8V and not 3.3V input
    2. profile pins <2:0> = 000.
    3. Can we change your Icp to 387uA. CFR3<21:19>=111b

    Let me know if you've verified them.

  • Thanks for your reply!

    Yes, my PDCLK pin has no expected signal in QDUC mode. In my QDUC mode, the PDCLK pin is always logic low, despite the fact that the PDCLK enable bit has been set as logic high. My control words are as follows (I use the crystal resonator on the backside of the board, 25MHz):

    CFR1: 0x0000 0000;     //QDUC mode

    CFR2: 0x0040 0820;     //PDCLK is enabled

    CFR3: 0x1a1f 4130;      //multiplication factor is 24, then the SYSCLK = 24*25 = 600 MHz,

    Profile0: 0x3cb5 0000 2000 0000     //DDS output is 75MHz. CC Interpolation Rate is 15, so the PDCLK = 600/(2*15) = 20 MHz;

    Thanks!

  • Yes, I have populated the loop filter components, and the PLL_LOCK pin is logic high. Besides, I get the right SYSCLK. But, still the PDCLK pin has no signal.

    Thanks!