AD9854 controller in VHDL

Hello.

I have troubles with programming AD9854 DDS through SPI interface. It is necessary to realize a chirp signal generation but first, I decided to try the easiest option — single tone mode of AD9854. There are 80 MHz oscillator and Altera CPLD as controller. As I understood from the datasheet, I have to send the Master Reset signal (10 or more REFCLK periods) and then send an address and a value of FTW1. So, for 20 MHz sine wave FTW1 value should be "x0400000000000".

I made the VHDL description, but it doesn't work. Here is the waveform obtained in the simulation:

There is mosi signal which contains:

Address of Control Register: "00000111";

Control Register data: b"00010000_01100000_00010001_00000000";

FTW1 address: "00000010"

FTW1 data: x"0400000000000"

So, I have some questions:

1) Is it necessary to send Update Clock signal (I/O UD CLK)? I noticed that the DDS produces it internally by default. In addition, I can't control REFCLK signal to enable it after Control Register programming (and switch to external Update Clock mode) as described in the datasheet.

2) Is it enough to just send the Master Reset signal and change the value of FTW1 to receive anything from AD9854?

3) Is it acceptable to place my VHDL code here?

4) Could anybody post any example of controlling AD9854 in VHDL please?

Thanks in advance.

P.S. Sorry for my poor english.

  • 0
    •  Analog Employees 
    on Sep 12, 2013 2:30 AM

    Hi,

    What do you mean by:

    I made the VHDL description, but it doesn't work.

    Do you mean, there is no DDS output of 20MHz?

    Before we proceed with the software level, can we isolate first the hardware issues (if there's any). Are you using the AD9854 evaluation board? or your own board?

    If your own board, kindly verify if you have tied pin 70 (S/P SELECT) pin to gnd. And check if you have the same settings on the Serial I/O pin requirements found in Table 9.

    Thanks.

  • Sorry for the incorrect question.

    I mean, there isn't any signal from the DDS after programming the controller (Altera CPLD). The hardware is OK, although it's not the evaluation board.

    S/P SELECT pin is connected directly to controller's pin and it is always in "low" state.

  • 0
    •  Analog Employees 
    on Sep 18, 2013 10:14 PM

    Hi,

    I apologize for the late follow-up.

    Would it be ok to have a look at your schematic (esp AD9854 part)? I would just like to isolate the pin connection issue of AD9854.

    To answer some of your questions:

    1) Is it necessary to send Update Clock signal (I/O UD CLK)?

         No, since by default the I/O UD CLK is internally generated, this means you should get and I/O UPDATE at the appropriatee rate after master reset (default is 40h).

    2) Is it enough to just send the Master Reset signal and change the value of FTW1 to receive anything from AD9854?

         Yes, just as long as you are sure that the I/O UD CLK is toggling. Can you check the output of pin 20 (I/O UD CLK)?

    In addition, I'm no expert of VHDL but I have 1 customer before that the problem was about VHDL compilation. That too is worth checking.

    Thanks,

    Sittie

  • 0
    •  Analog Employees 
    on Oct 23, 2013 5:11 PM

    Hi,

    Using serial port, the AD9854 can support MSB-first or LSB-first data formats. This is controlled by Bit 1 of the Control register. The default is low, that is the MSB-first format.

  • Hi guys,

    I am having similar trouble getting this chip to program. I am using SPI and I am trying to shut down the internal update clock but my control byte has no effect. Which bytes should be sent first high bytes or low bytes first.

    Instruction_Data

    Ronan