I have troubles with programming AD9854 DDS through SPI interface. It is necessary to realize a chirp signal generation but first, I decided to try the easiest option — single tone mode of AD9854. There are 80 MHz oscillator and Altera CPLD as controller. As I understood from the datasheet, I have to send the Master Reset signal (10 or more REFCLK periods) and then send an address and a value of FTW1. So, for 20 MHz sine wave FTW1 value should be "x0400000000000".
I made the VHDL description, but it doesn't work. Here is the waveform obtained in the simulation:
There is mosi signal which contains:
Address of Control Register: "00000111";
Control Register data: b"00010000_01100000_00010001_00000000";
FTW1 address: "00000010"
FTW1 data: x"0400000000000"
So, I have some questions:
1) Is it necessary to send Update Clock signal (I/O UD CLK)? I noticed that the DDS produces it internally by default. In addition, I can't control REFCLK signal to enable it after Control Register programming (and switch to external Update Clock mode) as described in the datasheet.
2) Is it enough to just send the Master Reset signal and change the value of FTW1 to receive anything from AD9854?
3) Is it acceptable to place my VHDL code here?
4) Could anybody post any example of controlling AD9854 in VHDL please?
Thanks in advance.
P.S. Sorry for my poor english.