I am designing an ADC circuit for CCD, I am used ADC9822 and the circuit is exactly same as datasheet.
The sampling rate is 1.25MHz and ADC is programmed in single channel and CDS mode. The noise at the output is too much and I am losing 7 bits of the digital value. The attached file shows the digital output of the AD9822 while the analogue input is grounded.
Could you please help me to reduce the noise level in the output?
Also I need to mention that ARM cortex4 is used to generate required signals for ADC.
In addition to Harry's comments, you should also try adjusting the phase of the ADCCLK signal to see if the noise is reduced. The CDSCLK/ADCLK waveform quality is also important- you don't want to see any overshoot or ringing, so adding series resistance can help.
Have you tried looking at the frequency content of the noise plot using an FFT?