I am designing an ADC circuit for CCD, I am used ADC9822 and the circuit is exactly same as datasheet.
The sampling rate is 1.25MHz and ADC is programmed in single channel and CDS mode. The noise at the output is too much and I am losing 7 bits of the digital value. The attached file shows the digital output of the AD9822 while the analogue input is grounded.
Could you please help me to reduce the noise level in the output?
Also I need to mention that ARM cortex4 is used to generate required signals for ADC.
Thanks for your quick reply.
The PCB is two layers and I have separated digital part from analog part with LDO (LP2985-50).
Do you have any suggestion on designing PCB and reducing noise on power line?
It's probably not the part, but rather bypassing or pc board layout. How many layers is your pc board?
Schematic? Noise on power rails?
As I mentioned i have used 2 layers PCB board. I will use ADM7150, but for know how can i get ride of the noise?
Following is the schematic. peak to peak noise is about 10mv on ADC power supply line.
Take 2V FS and divide by 2^14. That's an LSB.
For a 14 bit system, I would start with a four layer board with a full layer for a ground plane.
Switch to a lower noise reg: ADM7150
" It's probably not the part, but rather bypassing or pc board layout. How many layers is your pc board?
Schematic? Noise on power rails?"
In addition to Harry's comments, you should also try adjusting the phase of the ADCCLK signal to see if the noise is reduced. The CDSCLK/ADCLK waveform quality is also important- you don't want to see any overshoot or ringing, so adding series resistance can help.
Have you tried looking at the frequency content of the noise plot using an FFT?