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AD9959 Zero Crossing BPSK Implementation


I've been trying to generate a zero-crossing BPSK signal and came across this:

Zero-Crossing FSK/PSK Modulator: Analog Dialogue: Analog Devices

This page describes method of implementation of FSK using AD9958, whereas I'm interested in BPSK with zero crossing. I have a DDS AD9959 board and need to understand detailed steps to implement this method. Any help in this matter is appreciated.



  • Any help in this matter would be greatly appreciated.

  • Hi,


    Sorry for late response. I think the same method for zero-crossing FSK is used for zero-crossing BPSK because the result for a zero-crossing BPSK is shown in Figure 8 of the article. The changes would be the FTW for the mark, space and GRR will now be 14bits MSB aligned in the profile register.


    Best regards,


  • Hey Mark thanks for the reply. What I think about this:

    The changes would be the FTW for the mark, space and GRR will now be 14bits MSB aligned in the profile register.

    the mark, space and GRR will be indeed be 14 bits (as CPOW= 14 bit) but that won't be loaded into FTW, rather that will go into CPOW.

    Here's what I think I should do, please correct me if I'm wrong:

    GRR = FS/2^n

    where my Fs= 160 MHz

    For a 180 degree phase I have Mark:      100000 00000000

    For a 0  degree phase I have Space:      000000 00000000

    GRR (Ch1)                                    :      100000 00000000

    which give n=14

    and correspondingly GRR=9765 HZ

    What should be the steps in harware and software following these calculations that should give me the desired BPSK with zero crossing. The article I mentioned doesn't go into detail about that.


  • We don't have this as a canned solution , it will require some work on your side, but I can get you started and should be able to help you if you run into issues.

    First off, your calculation for the GRR is incorrect, though it's understandable why.  Even though you are doing PSK instead of FSK, you still need to calculate the GRR based on the frequency tuning word of the base signal, not on the phase offset words you are toggling between.  So to establish N, find the least significant 1 in the FTW, and count the number of 0 value LSBs, and subtract that from 32.

    For example, if your tuning word is xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx1, n is 32 (worst case), whereas for a tuning word that fits the pattern:  xxxxxxxx xxxxxxxx xxxxxx10 0000000, the GRR is 23.

    You need to program an auxiliary DDS channel (I'll refer to it as the trigger channel) with an FTW that has all zeros EXCEPT for a single 1 in that same bit (for the GRR of 23 case, the tuning word would be 00000000 00000000 00000010 0000000.  The output of the trigger channel will be a very slow sinusoid, you will want to square that signal up.  There are less expensive options, but one possible solution is the ADCLK905.

    Feed this square wave back to your I/O update input, and you have the device set to trigger it's own change such that changes will always occur at the same phase state, but there are latencies in this system that need to be calibrated out in order to ensure this switch occurs at the zero crossing, you will have to do this in the lab.  This is done by adjusting the phase offset word (POW) of the trigger channel until you see the phase changes occur at the zero crossing.

    Load the Mark and Space offsets as POWs into two of the profiles for your primary output, then toggle the appropriate profile selection pin when you wish to shift between the two.  Now you find the right POW for the trigger channel through lab experiments.  Be sure to clear the phase accumulator for BOTH the primary and trigger channels at the same time before going through this, and after you have programmed in the FTWs for both channels, both when finding the right trigger POW to get zero crossing, and as part of your start up sequence.

    NOTE this will not necessarily result in the device toggling at the next zero crossing, it is likely to take many cycles on the output before it does toggle, and the number of cycles it will take will vary from one shift request to the next.  If your need is for a BPSK that respond quickly, or with a consistent latency, then we do not have a viable solution in our existing portfolio.

  • Similar situation, looking for zero crossing BPSK, First and multiple readings of the data sheet led me to believe that applying a modulation signal to a profile pin with the serial I/O configuration set to single tone mode 2 level phase would achieve this. Most of the time it does, but if the I/O_UPDATE is asynchronous to the SYNC_CLK ( which the evaluation board is), then if less than the set-up time window, it does not work. My SYNC_CLK is 40MHz, (25ns) so about 1 time in 6 it fails.

    A solution to use the SYNC_CLK output to ensure the I/O_UPDATE meets the set-up spec seems to be required. My I/O_UPDATE comes from a PSOC5 system so this requires minor hardware mods.

    I should point out that the 'zero-crossing' need not be exact and my application uses a common clock for the REF_CLK and the modulation input, ensuring that after the initial configuration the output is always correct. There is always a pipeline delay, but examining the eye plots there is very little jitter ( <5ns)

    I needed the 4 channels for synchronized signals, so the solution to use a channel as an exact 'zero' reference would mean an AD9958 synchronized to the AD9959 - which may have its own problems.