We plan to use several DDS (let's say 10) in one system.
All the DDS get the same profiles.
All the DDS get the same REF_CLK of 100Mhz via a CXO and a clock distribution device, all adjusted for 0 delay /squew between them. The Internal PLL is used and operating at 2.5Ghz.
When switching off the power of the DDS only and then switching ON:
1- Will each DDS return to its previous frequency, Phase and amplitude (profiles are saved) after each switch ON?
2- Will we see a difference between the 10 DDS after each swith OFF/ON?
3-4 Same question in case of using an external REF_CLK of 3.5Ghz (PLL is deactivated).
5-In addition, I cannot find any reference design using the SYNC_IN and SYNC_OUT for multi chip use. Can you pls send it?
6-Is it possible to route the PLL output to an external pin?
1/3) The register map is volatile memory, if the chip is powered off, you should not expect anything to come back up as it was when you left it. If you want to go into a mode where you can wake it up and have it still holding the values you want, I think your two options are the powerdown mode, or setting the FTW to zero, though for the latter, you would have to re-program the FTW when you wanted to start up again.
2/4) There may be slight differences. Specifically, the PLLs will likely not settle to the same phase, and if there is any skew between the ref_clk or the IO_UPDATE that triggers activation of whatever you program into the devices, then you may see some of the chips off a cycle (perhaps more)
5) Look to the AD9915 datasheet for more detail on how to implement multi-chip SYNC, keep in mind this function is only guaranteed to work up to 2.5 GSPS
6) Unfortunately, no, the PLL output cannot be routed to an output pin
As I understand, to sync multi AD9914, it has to run at 2.5 GHz. What sync/clock module (AD951x series, AD952x series) would you recommend clocking at 2.5 GHz?
Can this setup be realised by the available eval boards?