AD9852 Project


I am currently developing an academical and research project at UNIVERSIDAD CENTRAL DE VENEZUELA (Central University of Venezuela) involving one of your integrates, more specifically an AD9852 DDS as a BPSK modulator for a amateur radio band, therefore I have a couple of questions that I would really appreciate to be help with.

1) What values of jitter and rise edge for the reference external clock are recommended for minimum noise in the output (or noise figure for what it matters)

2) Just to be sure, is it entirely necessary for the data input (i.e. a serial stream via SPI interface) to be an even sub multiple of the reference clock (in this case, the reference clock obtained by multiplying the external clock) for the modulation to be accurate?

I’m also aware of the update clock function of the integrate, so for example, let’s say my system clock runs at 250MHz, my SPI data input goes at 10Mbps, and I do an external, interruption driven clock update for every byte send via SPI. Would this process be OK for a correct BPSK modulation, so I don’t lose any information by wrong sampling processes on the integrate?

3) In the evaluation board available for the AD9852 one can see that the anti aliasing filter used is a chebyshev-cauer. I’m aware that a flat response on the pass band is highly desirable, but this filter also has an overshoot higher than 10%. Would you consider a filter with this model to be desirable for modulation applications? In this case a BPSK modulator.

4) Finally, in the Analog Dialogue, Volume 46, Number 1, 2012 issue, the process for a zero crossing switching BPSK/FSK is discussed. It is easy to understand the concept of using dual channels and the Grand Repetition Rate (GRR) between Mark and Space to force the system to switch at zero crossing, but is far not clear how can one easily implement it with the available integrates. Since I’m using an AD9852 which have an additional control DAC I’m really interested in the actual process of implementing the zero crossing switching.

I would really appreciate any information about this issues that could be provided

Thanks in advance

  • 0
    •  Analog Employees 
    on Feb 1, 2016 6:46 PM

    Hi Alejandro

    1.) It would really depend on your application. If it is a modulation, it would depend to the modulation standard that you are trying to implement your application with. But for a start, you can use figure 19 of the datasheet (residual phase noise) as reference on deciding how clean your clock should be.

    2.) From what I understand, it's not necessary to run SPI in even sub multiple. When you you reconfigure the device while doing BPSK modulation is being performed I believe there won't be an interruption if the reconfigured registers doesn't have to do with the BPSK modulation (reconfiguring phase adjust would affect BPSK modulation),  Another way is to fill in the I/O buffers with the configuration you wanted and only issue I/O update when you're on your way to stop or change your modulation.

    3.) When the filter was designed, the goal in mind was to reject images but not to have a good linear phase response or best settling time performance. Thus, feel free to decide what kind of filter would best fit for your application.

    4.) As of the moment, I don't have additional info on that.

    Best Regards


  • 0
    •  Analog Employees 
    on Feb 2, 2016 7:35 PM

    We do not have an identified solution for zero crossing BPSK/FSK with the AD9852.  I think any such solution would require two AD9852's running from the same System Clock source in order to make it possible.

  • Thank you both for your feedback is really appreciated!


    I’m actually not sure if a coherent modulator can be implemented with the AD9852. In the Analog Dialogue, Volume 46, Number 1, 2012 issue, the author specifies that a single reference channel is needed for each individual channel in which the zero phase crossing wants to be implemented. Since the AD9852 has two frequency and two phase registers, one can be used for the carrier frequency at the DAC output and the other for the frequency of the GRR at the control DAC output.


    On this article the author works with dual channel interface, but it can be seen that each of those channels have their own reference output. Also he specifies that a single chip dual channel would have better performance than using an additional chip, like another DDS, to generate the reference output, since not only they share the same clock frequency reference, but also are on a single chip, avoiding some thermal and noise problems.


    What I don’t get is what comes next. Let’s say is possible to implement it on an AD9852, and that I pre charge the GRR as a FTW for the control DAC output. What would I do with that output so it can force my system to change phases at zero crossing?


    While this is not a direct application for the DDS synthesizers, it feels like it should be better documented (i.e. as an application note) since it’s an attractive application for these devices, also considering that a lot of the DDS functions are well documented, either in the datasheets or in the technical tutorial.


    Then again, thank you very much for your answers. Any additional help on this issue would be really appreciated

  • 0
    •  Analog Employees 
    on Feb 4, 2016 3:04 AM

    The problem with the AD9854 is that there are not two independent DDS channels within the chip.  The second phase and frequency register are not, by themselves, sufficient to enable the ZERO crossing shift.  You also need an auxiliary accumulator which can be used to tag the zero crossing based on the GRR.  While there is a second accumulator, it does not have the necessary hooks available to enable this.  Anyone looking to implement such a switch is better off working with either the AD9958 or AD9959, and using the app note you reference to help them implement it.

  • Hi. Is there any way to simulate this particular IC? (or any of the DDS solutions offered by AD). i'm aware there's a IBIS model available, but that would only work to characterize the I/O buffers electrically. What i'm asking is if there is some sort of SPICE model or something similar that can help me simulate this IC functionally (i want to simulate my whole project first, since acquiring the IC is really hard in my country and would take too long)