AD9954 synchronisation

Hi,

Assuming I have single ad9954 on my board and it doesn't need to be synchronized:

1) I plan to turn off sync_clk output, what should I do with sinc_in pin?

2) Which synchrinization mode I need to configure?

3) I drive IO_UPDATE from async uController, I can't meet setup/hold requirment vs sync_clk (I can only make it wide), I dont really care if the update will ocour on the current or next sync_clk, do u see any problem.

4) I plan to work with refclk=100MHz, sysclk=400MHz, my output will be a 100MHz +/- upto 20KHz. after updating new FTW, will it output drift smotohly?

BR,

Barak

  • 0
    •  Analog Employees 
    on Apr 12, 2016 11:26 PM

    I recommend pulling the SYNC IN high or low to avoid unplanned/undesired rising edges on that pin from initiating anything on chip.

    You shouldn't have to configure the synchronization mode at all, just leave it as default.

    If you do not care about the +/1 period uncertainty, then you shouldn't have any problem.

    DDS outputs don't inherently drift, they jump to their new states over a single clock cycle.  If that is undesirable, you can set the device up into a sweep mode, in which case you have a significant level of control over how long it takes for the output to transition (drift) to the new state.

  • Hi,

    1) I just wanted to clarify the dds output issue:

    Basically I'm using dac output to drive a  clk to a FPGA. From FPGA point of view there is now problem that the clock will "jump" from one freq to another over a single clock cycle, I just want to be sure it will have smooth phase, for example:

    assuming my current freq is 100MHz, that mean rising edge every 10nSec, assuming I will jump to a new freq of 101MHz (9.9nSec), will the new rising edge will be 9.9nSec from the last "old" rising edge or can be ealier thus "creating" a momentary much higher clk freq in FPGA point of view?

    2) what should I do (left open, pull up, pull low) with unused pins as:

    COMP_IN, COMP_IN~ = ?

    PS0,PS1 = ?

    3) In the evb schematic DVDD_1.8V & AVDD_1.8V are used from the same source without filtering (ferrite bead, coil, etc'...). Dont u reccomend such a filtering?

    4) Can IO_UPDATE can be performed over SPI ("SW" update) or the only option is IO_UPDATE over pin?

    BR,

    Barak

  • Hi,

    1) I just wanted to clarify the dds output issue:

    Basically I'm using dac output to drive a  clk to a FPGA. From FPGA point of view there is now problem that the clock will "jump" from one freq to another over a single clock cycle, I just want to be sure it will have smooth phase, for example:

    assuming my current freq is 100MHz, that mean rising edge every 10nSec, assuming I will jump to a new freq of 101MHz (9.9nSec), will the new rising edge will be 9.9nSec from the last "old" rising edge or can be ealier thus "creating" a momentary much higher clk freq in FPGA point of view?

    2) what should I do (left open, pull up, pull low) with unused pins as:

    COMP_IN, COMP_IN~ = ?

    PS0,PS1 = ?

    3) In the evb schematic DVDD_1.8V & AVDD_1.8V are used from the same source without filtering (ferrite bead, coil, etc'...). Dont u reccomend such a filtering?

    4) Can IO_UPDATE can be performed over SPI ("SW" update) or the only option is IO_UPDATE over pin?

    BR,

    Barak

  • 0
    •  Analog Employees 
    on Apr 27, 2016 12:47 AM

    Sorry for the delay in responding to your last questions.

    I would pull the COMP_IN pins to opposite polarities.

    As for the Profile select pins, those should be pulled to the right state so that the correct profile is being selected from the register map.  If you are programming your desired state to Profile 0, then both PS1 and PS) should be pulled low.

    The onchip power scheme does a pretty good job of isolating the power planes, so you should be able to get good performance without separate ferrite beads, etc., but you may see some improvement by adding them.

    Unfortunately, IO_UPDATE cannot be implemented via a register write with the AD9954

    You should not get any runt pulses when changing frequency using the FTW; the DDS changes frequency in a phase continuous manner.  Referring to your specific example, you will likely see one pulse that is between 9.9 and 10.0 ns as you transition, but nothing outside that range of periods.

  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:26 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin