For the 6 to 8 MHzchirp needed for the receiver, we need to load a new frequency value everysample. This can be done by loading anew value into each of the two frequency registers every 2 samples andswitching the mux at the sysclock rate. This should be possible for the mux, not sure about loading thefrequency registers that fast as it seems you need to load an address followedby a data value each time – i.e. you need to lead addr1 data1 addr2 data2 atthe sysclock rate. The processor wouldhave to load a new value at the 30 MHz rate or every 33 nsec.
The question is can the frequency registers be programmedwith a new value at half the system rate which is 30MHz?
I haven't tried interfacing that kind of speed in the bus but will work in my assessment as long as you sustain the setup and hold time indicated by the datasheet (page 3).
Not sure I fully understand your question... Could you elaborate a little bit more, please?