Hi, on the AD9913, how much worse should the phase noise be when the PLL is engaged (2x multiplication) vs.

when it is direct fed? In this specific case:

Fref: 90 MHz  = sysclk


Fref: 90MHz using PLL=2x, 180 MHz = sysclk

For a FIXED output frequency, would there be a 20*log(2) degradation? That is not clear to me since the output frequency

is actually fixed.

The data sheet does not show this kind of comparison, only residual phase noise for direct fed and absolute

phase noise for PLL=4x.

Thanks, Jerry

  • Dear Louijie, I heard about this issue with the AD9913 DDS. Could you confirm and expand on this? We have been having some intermittent problems with the DDS.

    >>There is a well-known issue with the ADD9913 wherein the serial bus gets one bit off the message it's supposed to be receiving and then remains one bit off indefinitely.  He said there was a dedicated pin on the IC which issues a command to clear the SPI input buffer so that it can get back in sync with the master. 

    Do you know which pin is being referred to? We assumed it was not the master reset pin. Thanks,


  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:39 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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    EZ Admin