ad9913

Hi, on the AD9913, how much worse should the phase noise be when the PLL is engaged (2x multiplication) vs.

when it is direct fed? In this specific case:

Fref: 90 MHz  = sysclk

vs.

Fref: 90MHz using PLL=2x, 180 MHz = sysclk

For a FIXED output frequency, would there be a 20*log(2) degradation? That is not clear to me since the output frequency

is actually fixed.

The data sheet does not show this kind of comparison, only residual phase noise for direct fed and absolute

phase noise for PLL=4x.

Thanks, Jerry

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  • 0
    •  Analog Employees 
    on Dec 15, 2016 6:26 PM over 4 years ago

    The loop bandwidth of the PLL is based on the divide ratio of the VCO selection, and it  comes in two configurations, 100 Khz and 1 MHz loop BW. In this case it might happened that the BW being utilized by the device is 1 MHz. Any signal coming from the source which is less close to the loop bandwidth frequency would reflect to the output and will be amplified. In this case, 1.65 MHz offset is not a reference spur, it could be an interference signal coming from the supplies.

    Best Regards

    Louijie

Reply
  • 0
    •  Analog Employees 
    on Dec 15, 2016 6:26 PM over 4 years ago

    The loop bandwidth of the PLL is based on the divide ratio of the VCO selection, and it  comes in two configurations, 100 Khz and 1 MHz loop BW. In this case it might happened that the BW being utilized by the device is 1 MHz. Any signal coming from the source which is less close to the loop bandwidth frequency would reflect to the output and will be amplified. In this case, 1.65 MHz offset is not a reference spur, it could be an interference signal coming from the supplies.

    Best Regards

    Louijie

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