ad9913

Hi, on the AD9913, how much worse should the phase noise be when the PLL is engaged (2x multiplication) vs.

when it is direct fed? In this specific case:

Fref: 90 MHz  = sysclk

vs.

Fref: 90MHz using PLL=2x, 180 MHz = sysclk

For a FIXED output frequency, would there be a 20*log(2) degradation? That is not clear to me since the output frequency

is actually fixed.

The data sheet does not show this kind of comparison, only residual phase noise for direct fed and absolute

phase noise for PLL=4x.

Thanks, Jerry

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  • 0
    •  Analog Employees 
    on Nov 30, 2016 6:02 PM

    Hi Gerald,

    I did a set the evaluation board in bench and captured its phase noise under the conditions you've mentioned earlier. Kindly refer to the figures below.

    Phase noise at 90 MHz SYSCLK with 10 MHz fundamental

    Phase noise at 90 MHz SYSCLK with PLL 2x Enabled and a 10 MHz fundamental

    I hope this gave light to your inquiry. If there are is anything that you'd like to verify, don't hesitate to ask.

    Best Regards

    Louijie

Reply
  • 0
    •  Analog Employees 
    on Nov 30, 2016 6:02 PM

    Hi Gerald,

    I did a set the evaluation board in bench and captured its phase noise under the conditions you've mentioned earlier. Kindly refer to the figures below.

    Phase noise at 90 MHz SYSCLK with 10 MHz fundamental

    Phase noise at 90 MHz SYSCLK with PLL 2x Enabled and a 10 MHz fundamental

    I hope this gave light to your inquiry. If there are is anything that you'd like to verify, don't hesitate to ask.

    Best Regards

    Louijie

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