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No output for AD9910

Dear Sir/ Madam,

I encountered some issues when using DDS chip : DDS chip circuit is shown below , using FPGA   to control CSB,CLK,SDIO,IO-update pin . And the sequence diagram is shown in the following figure , using oscilloscope to probe tests : ref-clk=40M HZ, amplitude 1.8V, ref-clk-out output DC 1.8V,no output for sysnc-CLK . No signal on the output pin . I woner knowing the following questions :
1,Whether or not the input signals 40M HZ, 1.8V for ref-CLK meets AD9910's requirement , whehter or not no output for ref-CLK-out mean that the chips didn't work , or no output of sysnc-CLK ?
2,Whether or not the time series of FPGA has problems ( have little timing differences in PDF ) , why there is no output signal ? are R egisters not written in ?
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