AD5932 SPI polarity and phase

Hi Samuel Lourenço,

As a response for your questions:

1. The clock is active high (CPOL = 0). The datasheet indicates that SCK is high between write operations which is the same with the clock being active high.

2. Yes. The phase is trailing edge triggered (CPHA = 1)

Best regards,

Mark

Hi Mark,

So, the clock idles high between write operations, but idles low at the beginning and at the end of the transaction, right? I'm sorry, but It is not making much sense to me. Other sources show the clock idling low when CPOL is set to 0, but do not show the inter-byte state.

Kind regards, Samuel Lourenço

Hi Samuel Lourenço,

Apologies, I got confused with the statement on the data sheet regarding CPOL 0.

I thought this statement: "SCK idles high between write operations (CPOL = 0)", indicates that the active state of SCK is high or 1. This statement rather indicates that SCK idles high at the beginning and the end of the write operation or transaction which is CPOL 1 instead.

I'll try to verify this first and get back to you later. Thanks!

Best regards,

Mark

Hi Samuel Lourenço,

I've already confirmed this issue and there was a typo on the data sheet.

The correct polarity and phase is CPOL = 1 and CPHA = 0.

The data sheet is now being updated to reflect these corrections.

Thanks!

Best regards,

Mark

Thanks Mark,

That explains why I was not being able to control the AD5932. I was seeing the signals on my oscilloscope. I'll have to try the new settings.

Kind regards, Samuel Lourenço