PLL/DDS Frequency Sweep

Hi,

I am trying to make a small automated test equipment where i have a requirement to generate a sweep signal from 130MHz to 160MHz in steps of 25/12.5KHz for testing. The complete sweep time should be less than 5 seconds for the whole band. I tried achieving the same with ADF4351 EVAL Board, but it seems actual speed is limited by the usb and the step resolution by the loop filter value. i have several ideas but wanted to get some expert inputs on which approach is better in terms of ease of development without loosing accuracy.

1. What limits the ADF4351 to do the job. is it possible to make the sweep faster with 25KHz step spacing by changing the loop filter alone.

2. Will any other approach like using any DDS like ad9912 or 9957 help to make the sweep faster and accurate frequency  step.

3. What is the rate at which the dds can switch to different frequency, is it purely dependent on spi speed.

4. i am trying to avoid any use of mixer/upconversion techniques as i feel it make things more complex in terms of output spectrum.

5. if i use DDS, what is the simplest way to provide a relatively clean 1GHz signal.

Can anybody give hint on what could be the best approach/design with use of minimum components.

Thanks

Venkatesh

  • If you end up going to a DDS based solution, the AD9954, AD9911, ro AD9910 would be your most straightforward options for generating a sweep in that frequency range.  They use an auxiliary accumulator to implement the sweep.  The sweep rate and step size are programmable; it will likely be more easily and consistently controlled than a PLL based approach.

  • Hi JLKeip,

    Thankyou very much for your kind and prompt help.

    i would prefer AD9910 would be the most as i may need to increase the band upto 180 MHz later. i had a glance of the datasheet, seems i need to look for a good 10-25MHz source for driving the clock input by using internal PLL. Please let me know if any better ideas for the source possibly from ADI if any.

    In the DDS selection page of Analog devices, the output power of AD9910 is listed as 715mW, not sure if this is right. if it is, then that is very useful to me. Please confirm.

  • You'll find power specs on page 7 of the Rev E datasheet. The power number called out there is the typical value in single tone mode, if you are performing a frequency sweep, it will be a little higher due to the additional digital circuitry that is required to be on to implement the sweep function.

    The onboard REFCLK multiplier is not terribly high performance, if you wish to drive the DDS to better clock performance, I would look to the AD9525 or AD9530 for the lowest jitter clock generation from an ADI clock source.

    regards,

    Jeff

  • 0
    •  Analog Employees 
    on May 16, 2017 3:39 PM

    Hi ,

    A loop filter in the region of 100kHz can give you approx. 20usec lock time for the ADF4351...you can experiment with ADIsimPLL to work out optimum filter.

    A channel spacing of 25kHz for a hop of 30MHz is 1200 channels, so this is very achievable  from a loop filter / performance , then your write time needs to be within required time...

    We do have dedicated PLL s for ramping....HMC703...ADF4159

    Regards,

    Brigid.

  • Hi Brigid,

    i am trying to find a solution with minimal components, i believe, the part numbers listed by you have to be used with an external VCO. Do we have any other devices which has inbuilt ramp function and an integrated VCO as well.

    i tried simulating some parameters using ADIsim PLL as per your suggestion. As i already have two evaluation boards for adf4351. i was trying to simulate using the same device. got several doubts as listed down.

    1. i think that the PFD value should be equal to the maximum frequency hop that is possible, In my case the maximum frequency sweep will be 20 MHz with 25/12.5KHz spacing. Hence i have considered the PFD as 20 MHz.please let me know if i am wrong here. (loop filter BW of 100KHz)

    But in the simulation, if i select PFD as 20 MHz then, it does not allow 25MHz ref input clock to be taken which is available on the evaluation board. I have tried changing the PFD value to 10 MHz and it works (changed the prescaler according to get the right channel spacing).

    2. So if i select the PFD as 10 MHz and assume i wish to do a sawtooth profile of the frequency sweep, such that the sweep is repeated from the start frequency again. will this cause an issue.....

    Thanks