AD9910 Chip Synchronization problem

Hello

I trying to synchronzie 4 DDS of AD9910 ,but i am not yet there, i aligned the REFCLK of all of them

also the Sync out of the Master is connected to all the slaves by ADCLK846, I have made the SMP_ERR

Latch error bit go to 0 v. and for a minute every thing was aligned also at the Signal output, but when i changed 

frequency it didn't save the alignement. I0_Updated is triggered to all the DDS's at once every update, even when one DDS recives information to the register all of the DDS'S get IO_UPDATE. but still at every frequency different phase between the signals and also sometimes one frequency that was aligned after changing the frequency and going back to it ,changes the phase alignment a little.

is someone familiar with this sequence

Thank You in advane

Mier

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  • The SYNC preset register function is described at the bottom of page 44 of the Rev E datasheet.

    if your SYNC_CLK signals are not aligned, then yes, that can and likely will result in the type of behavior you are seeing.  I recommend using the Input sync receiver delay bits to compensate for the variance you are seeing in the SYNC CLK edges at the devices.  It is more important to have coincident SYNC_CLK edges than it is to have coincident I/O UPDATE edges.  The I/O Update signal triggers the update on the rising edge of the next SYNC CLK,

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  • The SYNC preset register function is described at the bottom of page 44 of the Rev E datasheet.

    if your SYNC_CLK signals are not aligned, then yes, that can and likely will result in the type of behavior you are seeing.  I recommend using the Input sync receiver delay bits to compensate for the variance you are seeing in the SYNC CLK edges at the devices.  It is more important to have coincident SYNC_CLK edges than it is to have coincident I/O UPDATE edges.  The I/O Update signal triggers the update on the rising edge of the next SYNC CLK,

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