AD9910 Chip Synchronization problem


I trying to synchronzie 4 DDS of AD9910 ,but i am not yet there, i aligned the REFCLK of all of them

also the Sync out of the Master is connected to all the slaves by ADCLK846, I have made the SMP_ERR

Latch error bit go to 0 v. and for a minute every thing was aligned also at the Signal output, but when i changed 

frequency it didn't save the alignement. I0_Updated is triggered to all the DDS's at once every update, even when one DDS recives information to the register all of the DDS'S get IO_UPDATE. but still at every frequency different phase between the signals and also sometimes one frequency that was aligned after changing the frequency and going back to it ,changes the phase alignment a little.

is someone familiar with this sequence

Thank You in advane


  • 0
    •  Analog Employees 
    on May 21, 2017 10:32 PM

    Hi Mier,

    I think you also have to align SYNC_CLK and provide a coincident IO_UPDATE to all the DDS.

    This application note might help.

    Best regards,


  • Hello Mark

    I have tried to align the Sync clock ,it seems they have about  0.5ns to 1ns difference,not shore if that is

    important ? the IO_UPADTE in my system are all coincident.

    what is this Sync preset registed , tried to write to eat didn't see too match affect.

    is there a more detailed procedure



  • The SYNC preset register function is described at the bottom of page 44 of the Rev E datasheet.

    if your SYNC_CLK signals are not aligned, then yes, that can and likely will result in the type of behavior you are seeing.  I recommend using the Input sync receiver delay bits to compensate for the variance you are seeing in the SYNC CLK edges at the devices.  It is more important to have coincident SYNC_CLK edges than it is to have coincident I/O UPDATE edges.  The I/O Update signal triggers the update on the rising edge of the next SYNC CLK,

  • Hello JLK

    I am trying to align the sync_clk with the recieve delay, 

    also to mention i had a point when i was working with Two DDS at let's say 80Mhz each ,and i have match the phase between them with the Recieve delay but, when i looked at Sync_clk they were unaligned. also when i moved to another frequency and came back it didn't save the phase alignment. maybe because of the preset register,it might have been on ,

    iam not shore.

     it seems also that sometimes the recieve delay give contribution and sometimes it's not,maybe because of the closed loop of the clocks at the master ?

    Thank you


  • The preset register is intended to inject some specific phased difference.  If you want them all sync'd, the make sure the preset registers are programmed the same on all the devices.  You'll need to determine the correct settings for the SYNC receive delays after doing that.