Hi,
I think there is an error on the AD9833 and AD9834 datasheets. Were it is written:
• SCK idles high between write operations (CPOL = 0)
• Data is valid on the SCK falling edge (CPHA= 1)
Should be:
• SCK idles high between write operations (CPOL = 1)
• Data is valid on the SCK falling edge (CPHA= 0)
This correction was already done on the AD5932 datasheet, that had the same error. Also, it makes sense that when the SCK idles high, it is active low, and therefore CPOL equals to 1. Given that, if the data is valid on the falling edge, in is now valid on the leading edge and not on the trailing edge, and hence CPHA equals to 0.
For the thread regarding the AD5932:
https://ez.analog.com/thread/93749-ad5932-spi-polarity-and-phase#comment-296065
Kind regards, Samuel Lourenço
